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cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 revision: v1.30 date: ??? i ? ??? ? 01 ? ??? i ? ??? ? 01 ?
rev. 1.30 ? ??? i ? ??? ? 01 ? rev. 1.30 3 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom table of contents eates cpu featu ? es ......................................................................................................................... 6 pe ? i ? he ? a ? featu ? es ................................................................................................................. 6 gene?a? desc?i?tion ......................................................................................... ? se?ection tab?e ................................................................................................. ? b?ock diag?am .................................................................................................. 8 pin ?ssignment ........... ..................................................................................... 8 pin desc?i?tion .......... ...................................................................................... 9 ?bso?ute maximum ratings .......................................................................... 10 d.c. cha?acte?istics ....................................................................................... 10 ?.c. cha?acte?istics ....................................................................................... 1? ?/d conve?te? cha?acte?istics ........... ........................................................... 13 powe? on reset e?ect?ica? cha?acte?istics .................................................. 14 bandga? refe?ence (vbg) cha?acte?istic cu?ve ......................................... 14 system ??chitectu?e ...................................................................................... 15 c ? ocking and pi ? e ? ining ......................................................................................................... 15 p ? og ? am counte ? ................................................................................................................... 16 stack ..................................................................................................................................... 1 ? ?? ithmetic and logic unit C ? lu ........................................................................................... 1 ? f?ash p?og?am memo?y ................................................................................. 18 st ? uctu ? e ................................................................................................................................ 18 s ? ecia ? vecto ? s ..................................................................................................................... 18 look-u ? tab ? e ............. ........................................................................................................... 18 tab ? e p ? og ? am exam ?? e ........................................................................................................ 19 in ci ? cuit p ? og ? amming ......................................................................................................... ? 0 on-chi ? debug su ?? o ? t C ocds ......................................................................................... ? 1 r?m data memo?y ......................................................................................... ?? st ? uctu ? e ................................................................................................................................ ?? s?ecia? function registe? desc?i?tion ........................................................ ?3 indi ? ect ? dd ? essing registe ? s C i ? r0 ? i ? r1 ......................................................................... ? 3 memo ? y pointe ? s C mp0 ? mp1 .............................................................................................. ? 3 bank pointe ? C bp ................................................................................................................. ? 4 ? ccumu ? ato ? C ? cc ............................................................................................................... ? 5 p ? og ? am counte ? low registe ? C pcl .................................................................................. ? 5 look-u ? tab ? e registe ? s C tblp ? tbhp ? tblh ..................................................................... ? 5 status registe ? C st ? tus .................................................................................................... ? 5
rev. 1.30 ? ???i? ??? ?01? rev. 1.30 3 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom eeprom data memory ........... ....................................................................... 27 eeprom data memo ? y st ? uctu ? e ........................................................................................ ?? eeprom registe ? s ............ .................................................................................................. ?? reading data f ? om the eeprom ......................................................................................... ? 9 w ? iting data to the eeprom ................................................................................................ ? 9 w ? ite p ? otection ..................................................................................................................... ? 9 eeprom inte ?? u ? t ............. ................................................................................................... ? 9 p ? og ? amming conside ? ations ............. ................................................................................... ? 9 p ? og ? amming exam ?? es ........................................................................................................ 30 oscillator ........................................................................................................ 31 osci ?? ato ? ove ? view ............. .................................................................................................. 31 system clock confgurations ................................................................................................ 31 exte ? na ? c ? ysta ? /ce ? amic osci ?? ato ? C hxt ........................................................................... 31 high s ? eed inte ? na ? rc osci ?? ato ? C hirc ........................................................................... 3 ? inte ? na ? 3 ? khz osci ?? ato ? C lirc ........................................................................................... 3 ? su ??? ementa ? y osci ?? ato ? ...................................................................................................... 3 ? operating modes and system clocks ......................................................... 33 system c ? ocks ...................................................................................................................... 33 system o ? e ? ation modes ...................................................................................................... 34 cont ? o ? registe ? .................................................................................................................... 35 fast wake-u ? ........................................................................................................................ 36 o ? e ? ating mode switching and wake-u ? .............................................................................. 3 ? norm ? l mode to slow mode switching ........................................................................... 38 slow mode to norm ? l mode switching ........................................................................... 39 ente ? ing the sleep0 mode .................................................................................................. 39 ente ? ing the sleep1 mode .................................................................................................. 40 ente ? ing the idle0 mode ...................................................................................................... 40 ente ? ing the idle1 mode ...................................................................................................... 40 standby cu ?? ent conside ? ations ........................................................................................... 41 wake-u ? ................................................................................................................................ 41 p ? og ? amming conside ? ations ............. ................................................................................... 4 ? watchdog timer ........... .................................................................................. 42 watchdog time ? c ? ock sou ? ce .............................................................................................. 4 ? watchdog time ? cont ? o ? registe ? ............. ............................................................................ 4 ? watchdog time ? o ? e ? ation ................................................................................................... 44 reset and initialisation .................................................................................. 45 reset ove ? view ..................................................................................................................... 45 reset functions ............. ....................................................................................................... 46 reset initia ? conditions ......................................................................................................... 49 input/output ports ......................................................................................... 51 pu ?? -high resisto ? s ................................................................................................................ 51 po ? t ? wake-u ? ............. ........................................................................................................ 5 ? i/o po ? t cont ? o ? registe ? s ..................................................................................................... 5 ?
rev. 1.30 4 ??? i ? ??? ? 01 ? rev. 1.30 5 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom pin- ? ema ?? ing functions ...................................................................................................... 53 pin- ? ema ?? ing registe ? s ....................................................................................................... 53 i/o pin st ? uctu ? es .................................................................................................................. 54 p ? og ? amming conside ? ations ............. ................................................................................... 55 timer modules C tm .......... ............................................................................ 55 int ? oduction ........................................................................................................................... 55 tm o ? e ? ation ............. ........................................................................................................... 56 tm c ? ock sou ? ce ............. ...................................................................................................... 56 tm inte ?? u ? ts ......................................................................................................................... 56 tm exte ? na ? pins ................................................................................................................... 56 tm in ? ut/out ? ut pin cont ? o ? registe ? s ............. .................................................................... 58 p ? og ? amming conside ? ations ............. ................................................................................... 58 compact type tm C ctm .............................................................................. 59 com ? act tm o ? e ? ation ......................................................................................................... 60 com ? act ty ? e tm registe ? desc ? i ? tion ................................................................................ 60 com ? act ty ? e tm o ? e ? ating modes .................................................................................... 65 com ? a ? e match out ? ut mode ............................................................................................... 65 time ? /counte ? mode ............................................................................................................. 68 pwm out ? ut mode ............. ................................................................................................... 68 analog to digital converter .......... ................................................................ 71 ? /d ove ? view ............. ........................................................................................................... ? 1 ? /d conve ? te ? registe ? desc ? i ? tion ...................................................................................... ? 1 ? /d conve ? te ? data registe ? s C ? drl ? ? drh ..................................................................... ?? ? /d conve ? te ? cont ? o ? registe ? s C ? dcr0 ? ? dcr1 ? ? cer ................................................. ?? ? /d o ? e ? ation ....................................................................................................................... ? 5 ? /d in ? ut pins ............. .......................................................................................................... ? 6 summa ? y of ? /d conve ? sion ste ? s ............. .......................................................................... ?? p ? og ? amming conside ? ations ............. ................................................................................... ? 8 ? /d t ? ansfe ? function ............. .............................................................................................. ? 8 ? /d p ? og ? amming exam ?? es ................................................................................................. ? 9 interrupts ........................................................................................................ 81 inte ?? u ? t registe ? s ................................................................................................................. 81 inte ?? u ? t o ? e ? ation ................................................................................................................ 85 exte ? na ? inte ?? u ? t ............. ...................................................................................................... 8 ? mu ? ti-function inte ?? u ? t .......................................................................................................... 8 ? ? /d conve ? te ? inte ?? u ? t ......................................................................................................... 8 ? time base inte ?? u ? ts ............................................................................................................. 88 eeprom inte ?? u ? t ............. ................................................................................................... 89 tm inte ?? u ? ts ......................................................................................................................... 89 inte ?? u ? t wake-u ? function ................................................................................................... 89 p ? og ? amming conside ? ations ............. ................................................................................... 90 confguration options ................................................................................... 91 application circuits ........... ............................................................................ 91
rev. 1.30 4 ???i? ??? ?01? rev. 1.30 5 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom instruction set ................................................................................................ 92 int ? oduction ........................................................................................................................... 9 ? inst ? uction timing .................................................................................................................. 9 ? moving and t ? ansfe ?? ing data ............................................................................................... 9 ? ?? ithmetic o ? e ? ations ............................................................................................................ 9 ? logica ? and rotate o ? e ? ation ............................................................................................... 93 b ? anches and cont ? o ? t ? ansfe ? ............................................................................................. 93 bit o ? e ? ations ....................................................................................................................... 93 tab ? e read o ? e ? ations ......................................................................................................... 93 othe ? o ? e ? ations ............. ...................................................................................................... 93 instruction set summary .......... .................................................................... 94 tab ? e conventions ................................................................................................................. 94 instruction defnition ..................................................................................... 96 package information ................................................................................... 105 8- ? in dip (300mi ? ) out ? ine dimensions ............................................................................... 106 8- ? in sop (150mi ? ) out ? ine dimensions ............................................................................. 10 ? 10- ? in msop out ? ine dimensions ...................................................................................... 108
rev. 1.30 6 ??? i ? ??? ? 01 ? rev. 1.30 ? ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom features cpu features ? operating v oltage f sys =8mhz: 2.2v~5.5v f sys =12mhz: 2.7v~5.5v f sys =16mhz: 3.3v~5.5v f sys =20mhz: 4.5v~5.5v ? up to 0.2s instruction cycle with 20mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? three oscillators external crystal C hxt internal rc C hirc internal 32khz rc C lirc ? multi-mode operation: normal, slow, idle and sleep ? fully integrated internal 4mhz, 8mhz and 12mhz oscillator requires no external components ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? 2-level subroutine nesting ? bit manipulation instruction peripheral features ? flash program memory: 0.5k16~1k16 ? ram data memory: 328~648 ? true eeprom memory: 328 ? watchdog t imer function ? 8 bidirectional i/o lines ? external interrupt line shared with i/o pin ? multiple t imer module for time measure, compare match output, pwm output functions ? dual t ime-base functions for generation of fxed time interrupt signals ? low voltage reset function ? multi-channel 12-bit resolution a/d converter ? package types: 8-pin dip/sop and 10-pin msop
rev. 1.30 6 ???i? ??? ?01? rev. 1.30 ? ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom general description the devices are flash memory with 8-bit high performance risc architecture microcontrollers. offering use rs t he c onvenience of fl ash me mory m ulti-programming fe atures, t hese de vices a lso include a wide range of functions and features. other memory includes an area of ram data memory as well as an area of true eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog features include a multi-channel 12-bit a/d converter function. multiple and extremely fexible t imer modules provide tim ing, and pwm generation function s. protective features such as an internal w atchdog t imer, low v oltage reset coupled with excellent nois e immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of hxt , hirc and lirc oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. the ability to operate a nd swi tch d ynamically b etween a r ange o f o perating m odes u sing d ifferent c lock so urces gives users the ability to optimise microcontroller operation and minimise power consumption. the inclusion of fexible i/o programming features, t ime-base functions along with many other features e nsure t hat t he de vices wi ll fnd e xcellent use i n a pplications suc h a s e lectronic m etering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. selection table most f eatures a re c ommon t o a ll d evices, t he m ain f eature d istinguishing t hem i s t he me mory capacity only. the following table summarises the main features of each device. part no. v dd program memory data memory data eeprom i/o ext. interrupt a/d timer module stack package HT66F005 ? . ? v~ 5.5v 0.5k16 3 ? 8 3 ? 8 8 1 1 ? -bit4 10-bit ctm ? ? 8dip/sop 10msop ht66f006 ? . ? v~ 5.5v 1k16 648 3 ? 8 8 1 1 ? -bit4 10-bit ctm ? ? 8dip/sop 10msop
rev. 1.30 8 ??? i ? ??? ? 01 ? rev. 1.30 9 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom block diagram
? ? ? ?? ? -? ? ? - ? ?

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? ? ? -? pin assignment

note: 1. bracketed pin names indicate non-default pinout remapping locations. 2. if the pin-shared pin functions have multiple outputs simultaneously , its pin names at the right side of the / sign can be used for higher priority. 3. vdd&a vdd means the vdd and a vdd are the double bonding.
rev. 1.30 8 ???i? ??? ?01? rev. 1.30 9 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom pin description with the exception of the power pins, all pins on these devices can be referenced by their port name, e.g. p a.0, p a.1 etc, which refer to the digital i/o function of the pins. however these port pins are also shared with other function such as the analog to digital converter , t imer module pins etc. the function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. pin name function op i/t o/t pin-shared mapping p ? 0~p ?? po ? t ? p ? w u p ? pu st cmos ? n0~ ? n3 ? /d conve ? te ? in ? ut ? cer ? n p ? 0~p ? 3 vref ? /d conve ? te ? ? efe ? ence in ? ut ? dcr1 ? n p ? 1 tck0 tm0 in ? ut prm st p ? 6 o ? p ?? tck1 tm1 in ? ut prm st p ?? o ? p ? 4 o ? p ?? tp0_0 tm0 i/o prm st cmos p ?? o ? p ? 0 tp0_1 tm0 i/o prm st cmos p ? 5 o ? p ? 1 tp1_0 tm1 i/o prm st cmos p ?? o ? p ? 6 tp1_1 tm1 i/o prm st cmos p ? 4 int exte ? na ? inte ?? u ? t intc0 integ st p ?? o ? p ? 5 o ? p ? 3 o ? p ?? osc1 hxt ? in co hxt p ? 6 osc ? hxt ? in co hxt p ? 5 vdd powe ? su ??? y* pwr ? vdd ? /d conve ? te ? ? owe ? su ??? y* pwr vss g ? ound** pwr ? vss ? /d conve ? te ? g ? ound** pwr note: i/t: input type; o/t: output type op: optional by confguration option (co) or register option pwr: power; co: confguration option; st: schmitt t rigger input cmos: cmos output; an: analog input pin hxt: high frequency crystal oscillator *: vdd is the device power supply while a vdd is the adc power supply . the a vdd pin is bonded together internally with vdd. **: vss is the device ground pin while a vss is the adc ground pin. the a vss pin is bonded together internally with vss.
rev. 1.30 10 ??? i ? ??? ? 01 ? rev. 1.30 11 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom absolute maximum ratings supply v oltage .............. .................................................................................. v ss ?0.3v to v ss +6.0v input v oltage .............. .................................................................................... v ss ? 0.3v to v dd +0.3v storage t emperature ............... ..................................................................................... -50? c to 125?c operating t emperature .............. .................................................................................... -40? c to 85 ?c i oh t otal .............. .................................................................................................................... -100ma i ol t otal .............. ..................................................................................................................... 100ma total power dissipation .............. .......................................................................................... 500mw note: t hese a re st ress ra tings onl y. st resses e xceeding t he ra nge spe cified und er "absol ute ma ximum ratings" m ay c ause su bstantial d amage t o t hese d evices. fu nctional o peration o f t hese d evices a t other c onditions be yond t hose l isted i n t he spe cifcation i s no t i mplied a nd pr olonged e xposure t o extreme conditions may affect devices reliability. d.c. characteristics 7d & symbol parameter test conditions min. typ. max. unit v dd conditions v dd o ? e ? ating vo ? tage (hxt) f sys =8mhz ? . ? 5.5 v f sys =1 ? mhz ? . ? 5.5 v f sys =16mhz 3.3 5.5 v f sys = ? 0mhz 4.5 5.5 v o ? e ? ating vo ? tage (hirc) f sys =8mhz ? . ? 5.5 v f sys =1 ? mhz ? . ? 5.5 v f sys =16mhz 3.3 5.5 v i dd1 o ? e ? ating cu ?? ent ? no ? ma ? mode ? f sys =f h (hxt) 3v no ? oad ? f h =4mhz ? ? dc off ? wdt enab ? e 0.6 0.9 m ? 5v 1.8 ? . ? m ? 3v no ? oad ? f h =8mhz ? ? dc off ? wdt enab ? e 1.1 1. ? m ? 5v ? .9 4.4 m ? 3v no ? oad ? f h =1 ? mhz ? ? dc off ? wdt enab ? e 1.6 ? .5 m ? 5v 4.1 6. ? m ? 3.3v no ? oad ? f h =16mhz ? ? dc off ? wdt enab ? e ? .0 3.0 m ? 5v 5. ? ? .8 m ? 5v no ? oad ? f h = ? 0mhz ? ? dc off ? wdt enab ? e 6.4 9.6 m ? i dd ? o ? e ? ating cu ?? ent ? no ? ma ? mode ? f sys =f h (hirc) 3v no ? oad ? f h =4mhz ? ? dc off ? wdt enab ? e 0.6 0.9 m ? 5v 1.8 ? . ? m ? 3v no ? oad ? f h =8mhz ? ? dc off ? wdt enab ? e 1.1 1. ? m ? 5v ? .9 4.4 m ? 3v no ? oad ? f h =1 ? mhz ? ? dc off ? wdt enab ? e 1.6 ? .5 m ? 5v 4.1 6. ? m ? i dd3 o ? e ? ating cu ?? ent ? s ? ow mode ? f sys =f l =lirc 3v no ? oad ? f sys =lirc ? ? dc off ? wdt enab ? e ? lvr disab ? e 10 ? 0 5v 30 50 i dd3 ? o ? e ? ating cu ?? ent ? s ? ow mode ? f sys =f l =lirc 3v no ? oad ? f sys =lirc ? ? dc off ? wdt enab ? e ? lvr enab ? e 40 60 5v 90 135
rev. 1.30 10 ???i? ??? ?01? rev. 1.30 11 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom symbol parameter test conditions min. typ. max. unit v dd conditions i dd4 o ? e ? ating cu ?? ent ? no ? ma ? mode ? f h =1 ? mhz (hirc) 3v no ? oad ? f sys =f h / ?? ? dc off ? wdt enab ? e 1. ? ? .4 m ? 5v ? .6 4.4 m ? 3v no ? oad ? f sys =f h /4 ? ? dc off ? wdt enab ? e 1.6 ? .4 m ? 5v ? .4 4.0 m ? 3v no ? oad ? f sys =f h /8 ? ? dc off ? wdt enab ? e 1.5 ? . ? m ? 5v ? . ? 3.6 m ? 3v no ? oad ? f sys =f h /16 ? ? dc off ? wdt enab ? e 1.4 ? .0 m ? 5v ? .0 3. ? m ? 3v no ? oad ? f sys =f h /3 ?? ? dc off ? wdt enab ? e 1.3 1.8 m ? 5v 1.8 ? .8 m ? 3v no ? oad ? f sys =f h /64 ? ? dc off ? wdt enab ? e 1. ? 1.6 m ? 5v 1.6 ? .4 m ? i dd5 o ? e ? ating cu ?? ent ? no ? ma ? mode ? f h =1 ? mhz (hxt) 3v no ? oad ? f sys =f h / ?? ? dc off ? wdt enab ? e 0.9 1.5 m ? 5v ? .5 3. ? 5 m ? 3v no ? oad ? f sys =f h /4 ? ? dc off ? wdt enab ? e 0. ? 1.0 m ? 5v ? .0 3.0 m ? 3v no ? oad ? f sys =f h /8 ? ? dc off ? wdt enab ? e 0.6 0.9 m ? 5v 1.6 ? .4 m ? 3v no ? oad ? f sys =f h /16 ? ? dc off ? wdt enab ? e 0.5 0. ? 5 m ? 5v 1.5 ? . ? 5 m ? 3v no ? oad ? f sys =f h /3 ?? ? dc off ? wdt enab ? e 0.49 0. ? 4 m ? 5v 1.45 ? .18 m ? 3v no ? oad ? f sys =f h /64 ? ? dc off ? wdt enab ? e 0.4 ? 0. ? 1 m ? 5v 1.4 ? .1 m ? i idle01 idle0 mode stanby cu ?? ent (lirc on) 3v no ? oad ? ? dc off ? wdt enab ? e 1.3 3.0 a 5v ? . ? 5.0 a i idle11 idle1 mode stanby cu ?? ent (hxt) 3v no ? oad ? ? dc off ? wdt enab ? e ? f sys =4mhz on 0.4 0.8 m ? 5v 0.8 1.6 m ? i idle11 ? idle1 mode stanby cu ?? ent (hirc) 3v no ? oad ? ? dc off ? wdt enab ? e ? f sys =4mhz on 0.4 0.8 m ? 5v 0.8 1.6 m ? i idle1 ? idle1 mode stanby cu ?? ent (hxt) 3v no ? oad ? ? dc off ? wdt enab ? e ? f sys =8mhz on 0.5 1.0 m ? 5v 1.0 ? .0 m ? i idle1 ?? idle1 mode stanby cu ?? ent (hirc) 3v no ? oad ? ? dc off ? wdt enab ? e ? f sys =8mhz on 0.8 1.6 m ? 5v 1.0 ? .0 m ? i idle13 idle1 mode stanby cu ?? ent (hxt) 3v no ? oad ? ? dc off ? wdt enab ? e ? f sys =1 ? mhz on 0.6 1. ? m ? 5v 1. ? ? .4 m ? i idle13 ? idle1 mode stanby cu ?? ent (hirc) 3v no ? oad ? ? dc off ? wdt enab ? e ? f sys =1 ? mhz on 0.6 1. ? m ? 5v 1. ? ? .4 m ? i idle14 idle1 mode stanby cu ?? ent (hxt) 3.3v no ? oad ? ? dc off ? wdt enab ? e ? f sys =16mhz on 1.0 ? .0 m ? 5v ? .0 4.0 m ? i idle15 idle1 mode stanby cu ?? ent (hxt) 5v no ? oad ? ? dc off ? wdt enab ? e ? f sys = ? 0mhz on ? .5 5.0 m ? i sleep0 sleep0 mode stanby cu ?? ent (lirc off) 3v no ? oad ? ? dc off ? wdt disab ? e ? lvr disab ? e 0.1 1.0 a 5v 0.3 ? .0 a i sleep1 sleep1 mode stanby cu ?? ent (lirc on) 3v no ? oad ? ? dc off ? wdt enab ? e ? lvr disab ? e 1.3 5.0 a 5v ? . ? 10 a
rev. 1.30 1 ? ??? i ? ??? ? 01 ? rev. 1.30 13 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom symbol parameter test conditions min. typ. max. unit v dd conditions v il1 in ? ut low vo ? tage fo ? i/o po ? ts o ? in ? ut pins 5v 0 1.5 v 0 0. ? v dd v v ih1 in ? ut high vo ? tage fo ? i/o po ? ts o ? in ? ut pins 5v 3.5 5.0 v 0.8v dd v dd v i ol i/o po ? t sink cu ?? ent 3v v ol =0.1v dd 4 8 m ? 5v v ol =0.1v dd 10 ? 0 m ? i oh i/o po ? t ? sou ? ce cu ?? ent 3v v oh =0.9v dd - ? -4 m ? 5v v oh =0.9v dd -5 -10 m ? r ph pu ?? -high resistance fo ? i/o po ? t s 3v ? 0 60 100 k 5v 10 30 50 k a.c. characteristics ta=25?c symbol parameter test conditions min. typ. max. unit v dd conditions f cpu o ? e ? ating c ? ock ? . ? v~5.5v dc 8 mhz ? . ? v~5.5v dc 1 ? mhz 3.3v~5.5v dc 16 mhz 4.5v~5.5v dc ? 0 mhz f sys system c ? ock (hxt) ? . ? v~5.5v 0.4 8 mhz ? . ? v~5.5v 0.4 1 ? mhz 3.3v~5.5v 0.4 16 mhz 4.5v~5.5v 0.4 ? 0 mhz f hirc system c ? ock (hirc) 3v/5v ta= ? 5c - ? % 4 + ? % mhz 3v/5v ta= ? 5c - ? % 8 + ? % mhz 5v ta= ? 5c - ? % 1 ? + ? % mhz 3v/5v ta=0~ ? 0c -5% 4 +5% mhz 3v/5v ta=0~ ? 0c -5% 8 +4% mhz 5v ta=0~ ? 0c -5% 1 ? +3% mhz ? . ? v~3.6v ta=0~ ? 0c - ? % 4 + ? % mhz 3.0v~5.5v ta=0~ ? 0c -5% 4 +9% mhz ? . ? v~3.6v ta=0~ ? 0c -6% 8 +4% mhz 3.0v~5.5v ta=0~ ? 0c -4% 8 +9% mhz 3.0v~5.5v ta=0~ ? 0c -6% 1 ? + ? % mhz ? . ? v~3.6v ta=-40c~85c -1 ? % 4 +8% mhz 3.0v~5.5v ta=-40c~85c -10% 4 +9% mhz ? . ? v~3.6v ta=-40c~85c -15% 8 +5% mhz 3.0v~5.5v ta=-40c~85c -8% 8 +9% mhz 3.0v~5.5v ta=-40c~85c -1 ? % 1 ? + ? % mhz f timer time ? i/p f ? equency ? . ? ~5.5v ? 8 mhz ? . ? ~5.5v ? 10 mhz 3.3~5.5v ? 1 ? mhz 4.5~5.5v ? 16 mhz
rev. 1.30 1? ???i? ??? ?01? rev. 1.30 13 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom symbol parameter test conditions min. typ. max. unit v dd conditions f lirc system c ? ock (lirc) 5v ta= ? 5c -10% 3 ? +10% khz t int inte ?? u ? t pu ? se width 1 t sys t lvr low vo ? tage width to reset 1 ? 0 ? 40 480 s t bgs vbg tu ? n on stab ? e time ? 00 s t sst system sta ? t-u ? time ? pe ? iod (wake-u ? f ? om h ? lt) f sys =xt ? l 10 ? 4 t sys f sys =hirc osc 15~16 f sys =lirc osc 1~ ? t rstd system reset de ? ay time (powe ? on reset) ? 5 50 100 ms system reset de ? ay time ( ? ny reset exce ? t powe ? on reset) 8.3 16. ? 33.3 ms 1rwh w sys i sys dd h dud i h hudo oodu iuhth d hso dsdu o h hh hhh d d odh d oh h hyh d soh a/d converter characteristics ta=25?c symbol parameter test conditions min. typ. max. unit v dd condition ? v dd ? /d conve ? te ? o ? e ? ating vo ? tage v ref= ? v dd ? . ? 5.5 v v ? di ? /d conve ? te ? in ? ut vo ? tage 0 v ref v v ref ? /d conve ? te ? refe ? ence vo ? tage ? ? v dd v dnl diffe ? entia ? non- ? inea ? ity 5v t ? dck =1.0s 1 + ? lsb inl integ ? a ? non- ? inea ? ity 5v t ? dck =1.0s ? +4 lsb i ? dc ? dditiona ? powe ? consum ? tion if ? /d conve ? te ? is used 3v no ? oad (t ? dck =0.5s) 0.90 1.35 m ? 5v no ? oad (t ? dck =0.5s) 1. ? 0 1.80 m ? t ? dck ? /d conve ? te ? c ? ock pe ? iod ? . ? ~5.5v 0.5 10 s t ? dc ? /d conve ? sion time (inc ? ude sam ?? e and ho ? d time) ? . ? ~5.5v 1 ? bit ? /d conve ? te ? 16 t ? dck t ? ds ? /d conve ? te ? sam ?? ing time ? . ? ~5.5v 4 t ? dck t on ? st ? /d conve ? te ? on-to-sta ? t time ? . ? ~5.5v ? s
rev. 1.30 14 ??? i ? ??? ? 01 ? rev. 1.30 15 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom power on reset electrical characteristics ta=25?c symbol parameter test conditions min. typ. max. unit v dd condition v por v dd sta ? t vo ? tage to ensu ? e powe ? -on reset 100 mv r por ? c v dd raising rate to ensu ? e powe ? -on reset 0.035 v/ms t por minimum time fo ? v dd to ? emain at v por to ensu ? e powe ? -on reset 1 ms bandgap reference (vbg) characteristic curve

rev. 1.30 14 ???i? ??? ?01? rev. 1.30 15 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom system architecture a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of devices take advantag e of the usual features found within ris c microcontrollers providing increas ed s peed of operation and enhanced performance. the pi pelining sc heme i s i mplemented i n suc h a wa y t hat i nstruction fe tching a nd i nstruction execution a re ove rlapped, he nce i nstructions a re e ffectively e xecuted i n one c ycle, wi th t he exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithm etic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addresse d. the simple addressi ng met hods of these registers along with additi onal architectural features ensure that a minimum of external components is required to provide a functional i/ o a nd a/ d c ontrol syst em wi th m aximum re liability a nd fe xibility. t his m akes t hese devices suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hxt , hirc or lirc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
? ? ? ? ? ? ? ? system clocking and pipelining
rev. 1.30 16 ??? i ? ??? ? 01 ? rev. 1.30 1? ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom
? ? ? ? ? ? ? ? ? ? instruction fetching program counter during pro gram e xecution, t he progr am co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. it is automatically incremented by one each time an instruction is e xecuted e xcept f or i nstructions, su ch a s jmp o r call t hat d emand a j ump t o a non-consecutive pr ogram me mory a ddress. on ly t he l ower 8 b its, k nown a s t he pr ogram c ounter low register, are directly addressable by the application program. when executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. device program counter high byte low byte (pcl register) HT66F005 pc8 pcl ? ~pcl0 ht66f006 pc9~pc8 pcl ? ~pcl0 program counter the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly; h owever, a s o nly t his l ow b yte is available for manipulation, the jumps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.30 16 ???i? ??? ?01? rev. 1.30 1 ? ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom stack this is a special part of the memory which is used to save the contents of the program counter only . the stack has two levels depending upon the devices and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allo wing the programmer to use the struct ure more easily . however , when the stack is full, a call subroutine instruction can still be execu ted which will result in a stack overfow . precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost.
device stack levels HT66F005 ? ht66f006 ? arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.30 18 ??? i ? ??? ? 01 ? rev. 1.30 19 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom flash program memory the program memory is the location where the user code or program is stored. for these devices series the program memory are flash type, which means it can be programmed and re-programmed a l arge num ber of t imes, a llowing t he use r t he c onvenience of c ode m odification on t he sa me device. by using the appropriate programming tools, these flash device s of fer users the fexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. structure the program memory has a capacity of 0.5k16 bits or 1k16 bits. the program memory is addressed by the program counter and also contains data, tabl e informati on and interrupt entries. table data, which can be setup in any location within the program memory , is addressed by a separate table pointer register. device capacity HT66F005 0.5k16 ht66f006 1k16
program memory structure special vectors within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h is reserved for use by these devices reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the "t abrd [m]" or "t abrdl [m]" instructions, respectively . when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data me mory r egister [ m] a s sp ecified i n t he i nstruction. t he h igher o rder t able d ata b yte f rom the program memory will be transferred to the tblh special register . any unused bits in this transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data fow of the look-up table.
rev. 1.30 18 ???i? ??? ?01? rev. 1.30 19 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom

table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is 300h which refers to the start address of the last page within the 1k words program memory of the device. the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 306h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the tabrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the t abrd [m] instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation.
rev. 1.30 ? 0 ??? i ? ??? ? 01 ? rev. 1.30 ?1 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a, 06h ; initialise low table pointer - note that this address ; is referenced mov tblp, a ; to the last page or present page mov a, 07h ; initialise high table pointer mov tbhp, a : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; data at program memory address 306h transferred to ; tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address 305h transferred to ; tempreg2 and tblh in this example the data 1ah is ; transferred to tempreg1 and data 0fh to register tempreg2 : : org 300h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : in circuit programming the p rovision o f fl ash t ype pr ogram me mory p rovides t he u ser wi th a m eans o f c onvenient a nd easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming o r u pgrading t he p rogram a t a l ater st age. t his enables product m anufacturers to e asily keep t heir m anufactured produc ts suppl ied wi th t he l atest progra m re leases wi thout re moval a nd re-insertion of the device. holtek writer pins mcu programming pins pin description icpd ? p ? 0 p ? og ? amming se ? ia ? data icpck p ?? p ? og ? amming c ? ock vdd vdd powe ? su ??? y vss vss g ? ound the program memory can be programmed serially in-circuit using this 4-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. t wo additional lines are required for the power supply and one line for the reset. the technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. during the programming proces s, taking control of the p a0 and p a7 pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins.
rev. 1.30 ?0 ???i? ??? ?01? rev. 1.30 ? 1 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom
note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf. on-chip debug support C ocds there is an ev chip which is used to emulate the ht66f00x device series. the ev chip device also provides an on-chip debug function to debug the devices during the development process. the ev chip and the actual mcu devices are almost functionally compatible except for on-chip debug function. users can use the ev chip device to emulate the real chip device behavior by connecting the ocdsda and ocdsck pins to the holtek ht -ide development tools. the ocdsda p in i s t he oc ds da ta/address i nput/output p in wh ile t he oc dsck p in i s t he oc ds clock input pin. when users use the ev chip for debugging, other functions which are shared with the ocdsda and ocdsck pi ns in the actual mcu devi ce will have no ef fect in the ev chip. however, the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp . for more detailed ocds information, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. holtek e-link pins ev chip pins pin description ocdsd ? ocdsd ? on-chi ? debug su ?? o ? t data/ ? dd ? ess in ? ut/out ? ut ocdsck ocdsck on-chi ? debug su ?? o ? t c ? ock in ? ut vdd vdd powe ? su ??? y gnd vss g ? ound
rev. 1.30 ?? ??? i ? ??? ? 01 ? rev. 1.30 ?3 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the frst of these is an area of ram, known as the special function data memory. here are located registers which are necessary for correct operation of the devices. many of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory , which is reserved for general purpose use. all locatio ns within this area are read and write accessible under program control. the o verall da ta me mory i s su bdivided i nto t wo b anks f or a ll t he d evices. t he sp ecial pu rpose da ta memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the dif ferent data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for all devices is the address 00h. device capacity bank 0 bank 1 HT66F005 3 ? 8 40h~5fh 40h eec ? egiste ? on ? y ht66f006 648 40h~ ? fh 40h eec ? egiste ? on ? y general purpose data memory structure

? ?
? ?

?? ?? - ?? ? ? HT66F005/ht66f006 special purpose data memory
rev. 1.30 ?? ???i? ??? ?01? rev. 1.30 ? 3 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom

general purpose data memory special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operatio n to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two me mory po inters, k nown a s mp0 a nd mp1 a re p rovided. t hese me mory po inters a re physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the releva nt indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specifed by the related memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according to bp register . direct addressing can only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. note that for this series of devices, the memory pointers, mp0 and mp1, are both 8-bit registers and used to access the data memory together with their corresponding indirect addressing registers iar0 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4.
rev. 1.30 ? 4 ??? i ? ??? ? 01 ? rev. 1.30 ?5 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom indirect addressing program example data .section data adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 'code' org 00h start: m ov a,04h ; setup size of block m ov block,a mov a ,offset ad res1 ; a ccumulator l oaded w ith f rst r am ad dress mov m p0,a ; s etup m emory po inter wi th f rst r am a ddress loop: clr i ar0 ; c lear t he d ata a t ad dress d efned b y m p0 i nc mp0 ; increment memory pointer s dz block ; check if last memory location has been cleared jm p loop continue: 7kh ld l h khh l kd l kh hdh k deh hhhfh l dh hflf 50 dhh bank pointer C bp )ru wklv vhulhv ri ghylfhv wkh dwd 0hpru lv glylghg lwr wzr ednv 6hohfwlj wkh uhtxluhg dwd 0hpru duhd lv dfklhyhg xvlj wkh dn 3rlwhu lw lv xvhg wr vhohfw dwd 0hpru dnv a 7kh dwd 0hpru lv llwldolvhg wr dn diwhu d uhvhw h[fhsw iru d : 7 wlphrxw uhvhw l wkh 3rzhu rz 0rgh l zklfk fdvh wkh dwd 0hpru edn uhpdlv xdi ihfwhg ,w vkrxog eh rwhg wkdw wkh 6shfldo )xfwlr dwd 0hpru lv rw di ihfwhg e wkh edn vhohfwlr zklfk phdv wkdw wkh 6shfldo )xfwlr 5hjl vwhuv fd eh df fhvvhg iurp zl wkl d edn l uhfwo dgguh vvlj wkh d wd 0h pru zloo dozdv uhvxow l dn ehlj dffhvvhg luuhvshfwlyh ri wkh ydoxh ri wkh dn 3rlwhu ffhvvlj gdwd iurp ednv rwkhu wkd dn pxvw eh lpsohphwhg xvlj lgluhfw dgguhvvlj bp register bit 7 6 5 4 3 2 1 0 name dmbp0 r/w r/w por 0 %lw a 8lpsohphwhg uhdg dv %lw dmbp0: 6hohfw dwd 0hpru dnv dn dn
rev. 1.30 ?4 ???i? ??? ?01? rev. 1.30 ? 5 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user defi ned regi ster and anot her, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to cont rol operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nter a nd i ndicates t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the "clr wdt" or "hal t" instruction. the pdf fag is af fected only by executing the "halt" or "clr wdt" instruction or during a system power-up.
rev. 1.30 ? 6 ??? i ? ??? ? 01 ? rev. 1.30 ?? ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cleared by a system power-up or executing the clr wdt or halt instruction. t o is set by a wdt time-out. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ? c c r/w r r r/w r/w r/w r/w por 0 0 x x x x "x" unknown bit 7, 6 unimplemented, read as 0 bit 5 to: w atchdog t ime-out fag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 pdf: power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov: overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z: zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac: auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c: carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.30 ?6 ???i? ??? ?01? rev. 1.30 ?? ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom eeprom data memory these d evices c ontain a n a rea o f i nternal e eprom da ta me mory. e eprom, wh ich st ands f or electrically e rasable progra mmable re ad onl y me mory, i s by i ts na ture a non-vol atile form of re-programmable memory , with data retention even when its power supply is removed. by incorporating this kind of data memory , a w hole new hos t of application pos sibilities are made available to the designer . the avail ability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eep rom d ata m emory capacity is 328 bits for this s eries of devices . u nlike the p rogram memory and ram data memory , the eeprom data memory is not directly mapped into memory space and is there fore not directly addressable in the same way as the other types of memory . read and w rite operatio ns to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. device capacity address ??? devices 3 ? 8 00h~1fh eeprom registers three registers control the overall operation of the internal eeprom data memory . these are the address register , eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same was as any other special function register . the eec register however , being located in bank1, cannot be addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register , iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register , bp, set to the value, 01h, before any operations on the eec register are executed. eeprom register list name bit 7 6 5 4 3 2 1 0 ee ? d4 d3 d ? d1 d0 eed d ? d6 d5 d4 d3 d ? d1 d0 eec wren wr rden rd eea register bit 7 6 5 4 3 2 1 0 name d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w por x x x x x x unknown bit 7~5 unimplemented, read as 0 bit 4~0 data eeprom address data eeprom address bit 4~bit 0
rev. 1.30 ? 8 ??? i ? ??? ? 01 ? rev. 1.30 ?9 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom eec register bit 7 6 5 4 3 2 1 0 name wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3 wren: data eeprom w rite enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr: eeprom w rite control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. bit 1 rden: data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero w ill inhibit d ata eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set hi gh by the applic ation program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time. eed register bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x unknown bit 7~0 data eeprom address data eeprom address bit 7~bit 0
rev. 1.30 ?8 ???i? ??? ?01? rev. 1.30 ? 9 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom reading data from the eeprom to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation i s e xecuted. t he a pplication pr ogram c an po ll t he rd bi t t o de termine whe n t he da ta i s valid for reading. writing data to the eeprom to wr ite da ta t o t he e eprom, t he wr ite e nable bi t, w ren, i n t he e ec re gister m ust frst be se t high to enable the w rite function. the eep rom addres s of the data to be w ritten mus t then be placed in the eea register and the data placed in the eed register . if the wr bit in the eec register is now set high, an internal write cycle will then be initiated. setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fni shed c an be i mplemented e ither by pol ling t he w r bi t i n t he e ec re gister or by usi ng t he eeprom i nterrupt. w hen t he wr ite c ycle t erminates, t he w r b it wi ll b e a utomatically c leared t o zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent w rite operation is provided in several ways . after the devices are powered-on the w rite enable bit in the control register will be cleared preventing any write operations. al so a t p ower-on t he b ank po inter, b p, wi ll b e r eset t o z ero, wh ich m ean t hat da ta memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the w rite enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must first be enabled by setting the dee bit in the relevant interrupt register . when an eeprom write cycle ends, the def request fag will be set. if the global and eeprom interrupts are enabled and the stack is not full, a jump to the associated interrupt vector will take place. when the interrupt is serviced the eeprom interrupt fag will be automatica lly reset. more details can be obtained in the interrupt section. programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensuring that the w rite enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. although certainly not necessary , consideration might be given in the application program to the checking of the validity of new write data by a simple read back process.
rev. 1.30 30 ??? i ? ??? ? 01 ? rev. 1.30 31 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom programming examples reading data from the eeprom C polling method mov a, ee prom_adres ; u ser d efned ad dress mov eea, a mov a, 0 40h ; s etup m emory p ointer m p1 mov mp1, a ; mp1 p oints t o e ec r egister mov a, 0 1h ; s etup b ank p ointer mov bp, a set iar1.1 ; s et r den b it, e nable r ead o perations set iar1.0 ; s tart r ead c ycle - s et r d b it back: sz iar1.0 ; c heck f or r ead c ycle e nd jmp back clr iar1 ; d isable e eprom r ead/write clr bp mov a, e ed ; m ove r ead d ata t o r egister mov read_data, a writing data from the eeprom C polling method mov a, ee prom_adres ; u ser d efned ad dress mov eea, a mov a, e eprom_data ; u ser d efned da ta mov eed, a mov a, 0 40h ; s etup m emory p ointer m p1 mov mp1, a ; m p1 p oints t o e ec r egister mov a, 0 1h ; s etup b ank p ointer mov bp, a set iar1.3 ; s et w ren b it, e nable w rite o perations set iar1.2 ; s tart w rite c ycle - s et w r b it back: sz iar1.2 ; c heck f or w rite c ycle e nd jmp back clr iar1 ; d isable e eprom r ead/write clr bp
rev. 1.30 30 ???i? ??? ?01? rev. 1.30 31 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom oscillator various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and registers. oscillator overview in additio n to being the source of the main system clock the oscillators also provide clock sources for t he w atchdog t imer a nd t ime b ase i nterrupts. e xternal o scillators r equiring so me e xternal components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. all oscillator options are selected through the configuration options. the higher frequency oscillators provide higher perform ance but ca rry wi th i t t he disadva ntage of higher power requirem ents, whil e t he opposite is of course true for the lower frequency oscillators. w ith the capability of dynamically switching between fast and slow system clock, these devices have the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. pins exte ? na ? c ? ysta ? hxt 400khz~ ? 0mhz osc1/osc ? inte ? na ? high s ? eed rc hirc 4 ? 8 ? 1 ? mhz inte ? na ? low s ? eed rc lirc 3 ? khz oscillator types system clock confgurations there are three methods of generating the system clock, two high speed oscillators and one low speed oscillator. the high speed oscillators are the external crystal/ceramic oscillator and the internal 4mhz, 8mhz or 12mhz rc oscilla tor. the low speed oscillator is an internal 32khz rc oscillator . selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2~cks0 bits in the smod register and as the system clock can be dynamically selected. the actual source oscillator used for the high speed s ystem clock is chos en us ing a conf guration option. t he osc 1 a nd osc 2 p ins a re u sed t o c onnect t he e xternal c omponents fo r t he e xternal crystal. the available selections for high speed and low speed oscillator s are therefore: hirc+lirc or hxt+lirc. external crystal/ceramic oscillator C hxt the e xternal cryst al/ceramic syst em osc illator i s one of t he hi gh fre quency osc illator c hoices, which is s elected via configuration option. f or mos t crystal os cillator configurations, the s imple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requiring extern al capacitors. however , for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur . the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer's specifcation. for oscillator stability and to minimise the ef fects of noise and crosstalk, it is important to ensure thatthe crystal and any associated resistors andcapacitors along with interconnectinglines are all located as close to the mcuas possible.
rev. 1.30 3 ? ??? i ? ??? ? 01 ? rev. 1.30 33 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom
? ? ?? crystal/resonator oscillator C hxt crystal oscillator c1 and c2 values crystal frequency c1 c2 1 ? mhz 0 ? f 0 ? f 8mhz 0 ? f 0 ? f 4mhz 0 ? f 0 ? f 1mhz 100 ? f 100 ? f note: c1 and c ? va ? ues a ? e fo ? guidance on ? y. crystal recommended capacitor values high speed internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the i nternal r c o scillator h as t hree fx ed f requencies o f e ither 4 mhz, 8 mhz o r 1 2mhz. de vice trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. note that if this internal system clock option is selecte d as the high speed oscilla tor, as it requires no external pins for its operation, i/o pins p a6 and pa5 can only be used as normal i/o pins. internal 32khz oscillator C lirc the internal 32khz system oscillator is the low frequency oscillator . it is a fully integrated rc osc illator wi th a t ypical fre quency of 32khz a t 5v , re quiring no e xternal c omponents for i ts implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. supplementary oscillator the low speed oscillator , in addition to providing a system clock source is also used to provide a c lock so urce t o t wo o ther d evice f unctions. t hese a re t he w atchdog t imer a nd t he t ime b ase interrupts.
rev. 1.30 3? ???i? ??? ?01? rev. 1.30 33 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red por table a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce ve rsa, l ower spe ed c locks re duce current consumption. as holtek has provided thes e devices with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the devices have many dif ferent clock sources for both the cpu and peripheral function operation. by providing the us er w ith a w ide range of clock options us ing conf guration options and regis ter programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency , f h , or low frequency , f l , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register. the high speed system clock can be sourced from either an hxt or hirc oscillator , selected via a confguration option. the low speed system clock source can be sourced from internal clock f l . if the f l is selected, it can be sourced by the lirc oscillator . the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64.

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?? ? ?? ? ?- ? ?? ?? ?? ?? ?? ? ? ? ? ? ? ? ??
? ? ?? ? ? ? ? ? ? ? ?? ? ?? - ? system clock confgurations note: when the system clock source f sys is switched to f l from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuits to use.
rev. 1.30 34 ??? i ? ??? ? 01 ? rev. 1.30 35 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom system operation modes there are six dif ferent modes of operation for the microcontroller , each one with its ow n special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, t he normal mode a nd sl ow mode . t he re maining four m odes, t he sl eep0, sleep1, idle0 and idle1 mode are used when the microcontroller cpu is switched of f to conserve power. operation mode description cpu f sys f lirc/ f sub norm ? l mode on f h ~f h /64 on slow mode on f l on idle0 mode off off on idle1 mode off on on sleep0 mode off off off sleep1 mode off off on ? normal mode as t he n ame sug gests t his i s o ne o f t he m ain o perating m odes wh ere t he m icrocontroller h as all of its functions operational and where the system clock is provided by one of the high speed oscillators. t his m ode ope rates a llowing t he m icrocontroller t o ope rate norm ally wi th a c lock source will come from one of the high speed oscillators, either the hxt or hirc oscillators. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register . although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. ? slow mode this is also a mode where the microcontroller operates normally although now with a slower speed clock source. the clock source used will be from the low speed oscillator , namely lirc. running the micro controller in this mode allows it to run with much lower operating currents. in the slow mode, f h is off. ? sleep0 mode the sleep mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is low . in the sleep0 mode the cpu will be stopped, and the f lirc clock will be stopped too, and the w atchdog t imer function is disabled. ? sleep1 mode the sleep mode is entered when an hal t instruction is executed and when the bit, idlen, in the smod register is low . in the sleep1 mode the cpu will be stopped. however the f lirc clock will continue to operate if the w atchdog t imer is enabled. ? idle0 mode the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is low . in the idle0 mode the system oscilla tor will be inhibit ed from driving the cpu but some peripheral functions will remain operational such as the t ime base and tms. in the idle0 mode, the system oscillator will be stopped.
rev. 1.30 34 ???i? ??? ?01? rev. 1.30 35 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom ? idle1 mode the idle1 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the t ime base and tms. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be the high or low speed system oscillator. in the idle1 mode the w atchdog t imer clock, f lirc , will be on. control register a single register, smod, is used for overall control of the internal clocks within these devices. smod register bit 7 6 5 4 3 2 1 0 name cks ? cks1 cks0 fsten lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 1 1 bit 7~5 cks2~cks0: the system clock selection when hlclk is 0 000: f l (f lirc ) 001: f l (f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in additio n to the system clock source the lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 fsten: fast w ake-up control (only for hxt) 0: disable 1: enable this is the fast w ake-up control bit which determines if the f lirc clock source is initially used after the device wake up. when the bit is high, the f lirc clock source can be used as a temporary system clock to provide a faster wake up time as the f lirc clock is available. bit 3 lto: low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscilla tor ready fag which indicates when the low speed system oscillator is stable after pow er on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode but after a wake-up has occurred, the fag will change to a high level after 1~2 clock cycles if the lirc oscillator is used. bit 2 hto: high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready fag which indicates when the high speed system oscillator is stable. this fag is cleared to 0 by hardware when the devices are powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as 1 by the application program after device power -on. the fag will be low when in the sleep or idle0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the hxt oscillator is used.
rev. 1.30 36 ??? i ? ??? ? 01 ? rev. 1.30 3? ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom bit 1 idlen: idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the hal t instruction is executed. if this bit is high, when a hal t instruction is executed the devices will enter the idle mode. in the idle1 mode the cpu will stop running but t he syst em c lock wi ll c ontinue t o ke ep t he pe ripheral fun ctions op erational, i f fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the devices will enter the sleep mode when a halt instruction is executed. bit 0 hlclk: system clock selection 0: f h /2~f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2~f h /64 or f l clock will be selected. when system clock switches from the f h clock to the f l clock and the f h clock will be automatically switched off to conserve power. fast wake-up to minimise power consumption the devices can enter the sleep or idle0 mode, where the system clock source to the devices will be stopped. however when the devices are woken up again, it can take a considerable time for the original system oscillator to restart, stabilize and allow normal operation t o re sume. t o e nsure t he de vices a re up a nd run ning a s fa st a s possi ble a fa st w ake-up function is provided, which allow f lirc , namely lirc oscillator , to act as a temporary clock to frst drive the system until the original system oscillator has stabilised. as the clock source for the fast wake-up function is f lirc , the fast w ake-up function is only available in the sleep1 and idle0 modes. when the devices are woken up from the sleep0 mode, the fast w ake-up function has no effect because the f lirc clock is stopped. the fast w ake-up enable/disable function is controlled using the fsten bit in the smod register. if the hxt oscil lator is sel ected as the normal mode syste m cl ock, and if the fa st w ake-up function is enabled, then it will take one to two t lirc clock cycles of the lirc oscillator for the system to wake-up. the system will then initially run under the f lirc clock source until 1024 hxt clock cycles have elapsed, at which point the ht o fag will switch high and the system will switch over to operating from the hxt oscillator. if the hirc oscillators or lirc oscillator is used as the system oscillator then it will take 15~16 clock c ycles of t he hirc or 1~2 c ycles of t he l irc t o wa ke up t he syst em from t he sl eep or idle0 mode. the fast w ake-up bit, fsten will have no effect in these cases. system oscillator fsten bit wake-up time (sleep0 mode) wake-up time (sleep1 mode) wake-up time (idle0 mode) wake-up time (idle1 mode) hxt 0 10 ? 4 hxt cyc ? es 10 ? 4 hxt cyc ? es 1~ ? hxt cyc ? es 1 10 ? 4 hxt cyc ? es 1~ ? f lirc cycles (system runs frst with f lirc fo ? 10 ? 4 hxt cyc ? es and then switches ove ? to ? un with the hxt c ? ock) 1~ ? hxt cyc ? es hirc x 15~16 hirc cyc ? es 15~16 hirc cyc ? es 1~ ? hirc cyc ? es lirc x 1~ ? lirc cyc ? es 1~ ? lirc cyc ? es 1~ ? lirc cyc ? es x: dont ca ? e wake-up times note that if the w atchdog t imer is disabled, which means that the lirc is of f, then there will be no fast w ake-up function available when these devices wake-up from the sleep0 mode.
rev. 1.30 36 ???i? ??? ?01? rev. 1.30 3 ? ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom
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operating mode switching and wake-up these devices can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the pres ent tas k in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the hal t instruction. when a hal t i nstruction i s e xecuted, whe ther t hese de vices e nter t he idl e mode or t he sl eep mode is determined by the condition of the idlen bit in the smod register and fsyson in the ctrl register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h, to the clock source, f h /2~f h /64 or f l . if the clock is from the f l , the high speed clock source will stop running to conserve power . when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may af fect the operation of other internal functions such as the tms. the accompanying fowchart shows what happens when these devices move between the various operating modes.
rev. 1.30 38 ??? i ? ??? ? 01 ? rev. 1.30 39 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes m ore powe r, t he syst em c lock c an swi tch t o run i n t he sl ow mode by se tting t he hlclk bit to 0 and setting the cks2~cks0 bits to 000 or 001 in the smod register . this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc oscillator and therefore requires these oscillators to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register.
? ?? ?? ??? ? ?? ?? ??? ? ? - ? ?? ?? ??? ? ? - ? ?? ?? ???
rev. 1.30 38 ???i? ??? ?01? rev. 1.30 39 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom
? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? - ? ? ?? ? ? ???? ? - ? ? ?? ? ? ? ?? ? slow mode to normal mode switching in the slo w mode the system uses the lirc low speed system oscillator . t o sw itch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to 1 or hlclk bit is 0, but cks2~cks0 is set to 010, 01 1, 100, 101, 1 10 or 1 11. as a cert ain amount of time will be required for the high frequency clock to stabilise, the status of the ht o bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. entering the sleep0 mode there is only one way for these devices to enter the sleep0 mode and that is to execute the halt instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 0 a nd t he wdt of f. when this instruction is executed under the conditions described above, the following will occur: ? the system clock, wdt clock and t ime base clock will be stopped and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared.
rev. 1.30 40 ??? i ? ??? ? 01 ? rev. 1.30 41 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom entering the sleep1 mode there is only one way for these devices to enter the sleep1 mode and that is to execute the halt instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 0 a nd t he wdt on. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock will be stopped and the application program will stop at the halt instruction, but the wdt will remain with the clock source coming from the f lirc clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f lirc clock as the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle0 mode there is only one way for these devices to enter the idle0 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in ctrl register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the hal t instruction, but the t ime base clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f lirc clock and the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle1 mode there is only one way for these devices to enter the idle1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in ctrl register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock and f sub clock will be on and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared.
rev. 1.30 40 ???i? ??? ?01? rev. 1.30 41 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of these devices to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit de signer i f t he powe r c onsumption i s t o be m inimised. spe cial a ttention m ust be m ade t o the i /o p ins o n t hese d evices. al l h igh-impedance i nput p ins m ust b e c onnected t o e ither a fx ed high or low level as any foating input pins could create internal oscillations and result in increased current consumpti on. this also applies to devices which have dif ferent package types, as there may be unbonded pins. these must eit her be set up as out puts or if set up as input s must have pul l-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the lirc oscillator is enabled. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator , the additional standby current will also be perhaps in the order of several hundred micro-amps. wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external reset ? an external falling edge on port a ? a system interrupt ? a wdt overfow if t he syst em i s woke n up by a n e xternal re set, t hese de vices wi ll e xperience a ful l syst em re set, however, i f t hese d evices a re wo ken u p b y a w dt o verflow, a w atchdog t imer r eset wi ll b e initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the t o and pdf fags. the pdf fag is cleared by a system power -up or executing the clear w atchdog t imer instructions and is set when executing the halt instruction. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wil l resume exec ution at the i nstruction f ollowing t he halt i nstruction. i f t he sy stem i s wo ken u p by a n i nterrupt, t hen two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the hal t instruction. in this situation, the interrupt which woke-up these devices will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled o r wh en a st ack l evel b ecomes f ree. t he o ther si tuation i s wh ere t he r elated i nterrupt i s enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request fag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled.
rev. 1.30 4 ? ??? i ? ??? ? 01 ? rev. 1.30 43 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom programming considerations the high speed and low speed oscillators both use the same sst counter. ? if these devices are woken up from the sleep1 mode to normal mode, and the system clock source is from hxt oscillator and fsten is 1, the system clock can be switched to the lirc oscillator after wake up. ? there are peripheral functions, such as wdt and tms, for which the f sys is used. if the system clock sourc e i s swi tched from f h t o f l , t he c lock sou rce t o t he pe ripheral func tions m entioned above will change accordingly. ? the on/of f conditi on of f sub and f s depends upon whether the wdt is enabled or disabled as the wdt clock source is selected from f lirc . watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer clock source is provided by the internal clock, f lirc , which is sourced from the lirc oscillator . the w atchdog t imer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer tim eouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register . the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v. however, it should be noted that this specifed internal clock period can vary with v dd , temperature and process variat ions. the wdt can be chosen using a confguration option to be always enabled or enabled/disabled using the wdtc register. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable/disable operation. the wrf software reset fag will be indicated in the ctrl register . this register together with a confguration option control the overall operation of the w atchdog t imer.
rev. 1.30 4? ???i? ??? ?01? rev. 1.30 43 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom wdtc register bit 7 6 5 4 3 2 1 0 name we4 we3 we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 we4~we0: wdt function software control if the wdt confguration option is selected as always enabled: 10101 or 01010: wdt enabled other values: reset mcu if the wdt confguration option is selected as controlled by the wdt control register: 10101: wdt disabled 01010: wdt enabled other values: reset mcu when t hese b its a re c hanged t o a ny o ther v alues d ue t o e nvironmental n oise t he microcontroller will be reset; this reset operation will be activated after 2~3 lirc clock cycles and the wrf bit in the ctrl register will be set to 1 to indicate the reset source. bit 2 ~ 0 ws2, ws1, ws0: wdt time-out period selection 000: 256/f lirc 001: 512/f lirc 010: 1024/f lirc 011: 2048/f lirc 100: 4096/f lirc 101: 8192/f lirc 110: 16384/f lirc 111: 32768/f lirc these three bits determine the divis ion ratio of the w atchdog t imer s ource clock, which in turn determines the timeout period. ctrl register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 bit 7 fsyson: f sys control in idle mode described elsewhere bit 6~3 unimplemented, read as 0 bit 2 lvrf: lvr function reset fag described elsewhere. bit 1 lrf: lvr control register software reset fag described elsewhere. bit 0 wrf: wdt control register software reset fag 0: not occurred 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application pr ogram. not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program.
rev. 1.30 44 ??? i ? ??? ? 01 ? rev. 1.30 45 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom watchdog timer operation the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the w atchdog t imer will overfow and reset the device. the w atchdog timer option, such as always enable or software control is selected using confguration option. w ith regard to the w atchdog t imer enable/disable function, there are also fve bits, we4~we0, in the wdtc register to offer additional enable/disable and reset control of the w atchdog t imer. wdt always enabled if the wdt configuration option has selected that the wdt is always enabled, the we4~we0 bits st ill ha ve a n e ffect on t he w dt func tion. w hen t he w e4~we0 bi t va lue i s e qual t o 01010b or 10101b, the wd t function is enabled. how ever, if the we4~we0 bits are changed to any other va lues e xcept 01010b a nd 10101b, whi ch m ay be c aused by e xternal i nfluences suc h a s environmental noise, it will reset the microcontroller after 2~3 lirc clock cycles. wdt enable/disabled using the wdt control register if the wdt configuration option has s elected that the wdt is enabled/dis abled us ing the wd t control register , the we4~we0 values can determine which mode the wdt operates in. the wdt will be disabled when the we4~we0 bits are set to a value of 10101b. the wdt function will be enabled if the we4~we0 bit value is equal to 01010b. if the we4~we0 bits are set to any other values ot her t han 01010b a nd 10101b, i t wi ll re set t he de vice a fter 2~3 l irc c lock c ycles. aft er power on these bits will have the value of 01010b. wdt confguration option we4 ~ we0 bits wdt function ?? ways enab ? ed 01010b o ? 10101b enab ? e ? ny othe ? va ? ue reset mcu cont ? o ?? ed by wdtc registe ? 10101b disab ? e 01010b enab ? e ? ny othe ? va ? ue reset mcu watchdog timer enable/disable control under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the w atchdog t imer contents. the frst is a wdt reset, which means a value other than 01010b or 10101b is written into the we4~we0 bit locations, the second is to use the w atchdog t imer software clear instructions and the third is via a hal t instruction. there is only one method of using software instruction to clear the w atchdog timer and that is to use the single clr wdt instruction to clear the wdt . the m aximum t ime out pe riod i s wh en t he 2 18 di vision ra tio i s se lected. as a n e xample, wi th t he 32khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration.
rev. 1.30 44 ???i? ??? ?01? rev. 1.30 45 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom clr wdtinst?uction 8-stage divide? wdt p?esca?e? we4~we0 bits wdtc registe? reset mcu lirc f s f lirc f s /? 8 8-to-1 mux clr ws?~ws0 (f s /? 8 ~ f s /? 18 ) wdt time-out (? 8 /f s ~ ? 18 /f s ) watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. a hardware reset will of course be automatically implemented after the device is powered-on, however there are a number of other hardware and software reset sources that can be implemented dynamically when the device is running. reset overview the most importa nt reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the microcontroller , after a short delay , will be in a well defned state and ready to execute the frst program instruction. after this power -on reset, certain important internal registers will be set to defned states before the program instructions commence execution. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. the devi ces provide several reset sources to gene rate the interna l reset signa l, providing extended mcu protection. the different types of resets are listed in the accompanying table. no. reset name abbreviation indication bit register notes 1 powe ? -on reset por ? uto gene ? ated at ? owe ? on ? low-vo ? tage reset lvr lrf ctrl low vdd vo ? tage 3 watchdog reset wdt to st ? tus 4 wtdc registe ? setting softwa ? e reset wrf ctrl w ? ite to wtdc ? egiste ? reset source summary
rev. 1.30 46 ??? i ? ??? ? 01 ? rev. 1.30 4? ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom reset functions there are several w ays in w hich a microcontroller res et can occur , through events occurring both internally and externally: ? power-on reset the most fundamental and unavoidable reset is the one that occurs afte r power is frst applied to the microcontroller. as well as ensuring that the program memory begins execution from the frst memory address, a power -on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. note: t rstd is power-on delay, typical time=50ms power-on reset timing chart ? low v oltage reset C lvr the micr ocontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device and provide an mcu reset should the value fall below a certain predefned level. the l vr function is always enabled with a specifc l vr voltage v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery in battery powered applications, the l vr will automatically reset the device internally and the lvrf bit in the ctrl register will also be set to 1. for a valid l vr signal, a low supply voltage, i.e., a v oltage i n t he r ange b etween 0 .9v~v lvr m ust e xist f or a t ime g reater t han t hat sp ecifed by t lvr i n t he a.c. c haracteristics. if t he l ow suppl y vol tage st ate doe s not e xceed t his va lue, the l vr wil l ignore the low supply vol tage and wil l not perform a reset functi on. the act ual v lvr value can be selected by the l vs bits in the l vrc register . if the l vs7~lvs0 bits are changed to some dif ferent values by environmental noise, the l vr will reset the device after 2~3 lirc clock cycles. when this happens, the lrf bit in the ctrl register will be set to 1. after power on the register will have the value of 01010101b. note that the l vr function will be automatically disabled when the device enters the power down mode. note: t rstd is power-on delay, typical time=16.7ms low voltage reset timing chart
rev. 1.30 46 ???i? ??? ?01? rev. 1.30 4 ? ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom lvrc register bit 7 6 5 4 3 2 1 0 name lvs ? lvs6 lvs5 lvs4 lvs3 lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~0 lvs7~lvs0: lvr v oltage select control 01010101: 2.1v 00110011: 2.55v 10011001: 3.15v 10101010: 3.8v any other value: generates mcu reset C register is reset to por value when an actual low voltage condit ion occurs, as specifed by one of the four defned lvr voltage values above, an mcu reset will be generated. the reset operation will be activated after 2~3 lirc clock cycles . in this s ituation the regis ter contents w ill remain the same after such a reset occurs. any register value, other than the four defned l vr values above, will also result in the generation of an mcu reset. the reset operation will be activated after 2~3 lirc clock cycles. however in this situation the register contents will be reset to the por value. ctrl register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 x 0 0 bit 7 fsyson: f sys control in idle mode describe elsewhere. bit 6~3 unimplemented, read as 0 bit 2 lvrf: lvr function reset fag 0: not occur 1: occurred this bit is set to 1 when a specifc low v oltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 lrf: lvr control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the l vrc register contains any non defned l vr voltage register values. this in ef fect acts like a software reset function. this bit can only be cleared to 0 by the application program. bit 0 wrf: wdt control register software reset fag describe elsewhere.
rev. 1.30 48 ??? i ? ??? ? 01 ? rev. 1.30 49 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom ? watchdog t ime-out reset during normal operation the w atchdog time-out reset during normal operation is the same as a power -on reset except that the w atchdog time-out fag t o will be set to 1. note: t rstd is power-on delay, typical time=16.7ms wdt time-out reset during normal operation timing chart ? watchdog t ime-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cle ared to 0 and the to fag will be set to 1. refer to the a.c. characteristics for t sst details. note: the t sst is 15~16 clock cycles if the system clock source is provided by hirc. the t sst is 1024 clock for hxt. the t sst is 1~2 clock for lirc. wdt time-out reset during sleep or idle timing chart wdtc register software reset a wdtc software reset will be generated when a value other than 10101 or 01010, exist in the highest fve bits of the wdtc register . the wrf bit in the ctrl register will be set high when this occurs, thus indicating the generation of a wdtc software reset. ? wdtc register bit 7 6 5 4 3 2 1 0 name we4 we3 we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 we4, we3, we2, we1, we0: wdt software control 10101: wdt disable 01010: wdt enable (default) other: mcu reset bit 2~0 ws2, ws1, ws0: wdt time-out period selection described elsewhere
rev. 1.30 48 ???i? ??? ?01? rev. 1.30 49 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus regis ter and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: to pdf reset conditions 0 0 powe ? -on ? eset u u lvr ? eset du ? ing norm ? l o ? slow mode o ? e ? ation 1 u wdt time-out ? eset du ? ing norm ? l o ? slow mode o ? e ? ation 1 1 wdt time-out ? eset du ? ing idle o ? sleep mode o ? e ? ation u stands fo ? unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p ? og ? am counte ? reset to ze ? o inte ?? u ? ts ??? inte ?? u ? ts wi ?? be disab ? ed wdt c ? ea ? afte ? ? eset ? wdt begins counting time ? modu ? es time ? counte ? wi ?? be tu ? ned off in ? ut/out ? ut po ? ts i/o ? o ? ts wi ?? be setu ? as in ? uts ? and ? n0~ ? n3 as ? /d in ? ut ? ins stack pointe ? stack pointe ? wi ?? ? oint to the to ? of the stack the dif ferent kinds of resets all af fect the internal registers of the microcontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will refect the situation for the larger package type.
rev. 1.30 50 ??? i ? ??? ? 01 ? rev. 1.30 51 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom register reset (power on) wdt time-out/wdtc software reset (normal operation) wdt time-out (halt)* i ? r0 0000 0000 0000 0000 uuuu uuuu mp0 xxxx xxxx uuuu uuuu uuuu uuuu i ? r1 0000 0000 0000 0000 uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu bp ---- ---0 ---- ---0 ---- ---u ? cc xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu tbhp ---- --xx ---- --uu ---- --uu st ? tus --00 xxxx --1u uuuu --11 uuuu smod 0000 0011 0000 0011 uuuu uuuu integ ---- --00 ---- --00 ---- --uu intc0 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 uuuu uuuu mfi0 --00 --00 --00 --00 --uu --uu mfi1 --00 --00 --00 --00 --uu --uu p ? 1111 1111 1111 1111 uuuu uuuu p ? c 1111 1111 1111 1111 uuuu uuuu p ? pu 0000 0000 0000 0000 uuuu uuuu p ? w u 0000 0000 0000 0000 uuuu uuuu prm 0000 0000 0000 0000 uuuu uuuu lvrc 0101 0101 0101 0101 uuuu uuuu wdtc 0101 0011 0101 0011 uuuu uuuu tbc 0011 -111 0011 -111 uuuu -uuu ctrl 0--- -x00 0--- -yyy u--- -uuu ee ? ---0 0000 ---0 0000 ---u uuuu eed 0000 0000 0000 0000 uuuu uuuu ? drl( ? drfs=0) xxxx ---- xxxx ---- uuuu ---- ? drl( ? drfs=1) xxxx xxxx xxxx xxxx uuuu uuuu ? drh( ? drfs=0) xxxx xxxx xxxx xxxx uuuu uuuu ? drh( ? drfs=1) ---- xxxx ---- xxxx ---- uuuu ? dcr0 0110 --00 0110 --00 uuu- uuuu ? dcr1 00-0 -000 00-0 -000 uuuu uuuu ? cer ---- 1111 ---- 1111 ---- uuuu tmpc ---- 0101 ---- 0101 ---- uuuu tm0c0 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 uuuu uuuu tm0dh ---- --00 ---- --00 ---- --uu tm0 ? l 0000 0000 0000 0000 uuuu uuuu tm0 ? h ---- --00 ---- --00 ---- --uu tm1c0 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 uuuu uuuu tm1dh ---- --00 ---- --00 ---- --uu tm1 ? l 0000 0000 0000 0000 uuuu uuuu
rev. 1.30 50 ???i? ??? ?01? rev. 1.30 51 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom register reset (power on) wdt time-out/wdtc software reset (normal operation) wdt time-out (halt)* tm1 ? h ---- --00 ---- --00 ---- --uu eec ---- 0000 ---- 0000 ---- uuuu note: - stands for not implement u stands for unchanged x stands for unknown y stands for "by register bit function" input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidi rectional input/out put li nes labeled with port names p a. this i/o port is mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. the i/o port can be used for input and output operations. for input operation, these ports a re non-l atching, whi ch m eans t he i nputs m ust be re ady a t t he t 2 ri sing e dge of i nstruction mov a, [m], where m denotes the port address. for output operatio n, all the data is latched and remains unchanged until the output latch is rewritten. i/o register list register name bit 7 6 5 4 3 2 1 0 p ? w u d ? d6 d5 d4 d3 d ? d1 d0 p ? pu d ? d6 d5 d4 d3 d ? d1 d0 p ? c d ? d6 d5 d4 d3 d ? d1 d0 p ? d ? d6 d5 d4 d3 d ? d1 d0 prm prms ? prms6 prms5 prms4 prms3 prms ? prms1 prms0 pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when configured as an input have the capability of being connected to an internal pull-high resistor . the p ull-high r esistor i s se lected u sing r egister, p apu, a nd i s i mplemented u sing we ak pmos transistors.
rev. 1.30 5 ? ??? i ? ??? ? 01 ? rev. 1.30 53 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom papu register bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 i/o port a bit 7~bit 0 pull-high control 0: disable 1: enable port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 pawu: port a bit 7~bit 0 w ake-up control 0: disable 1: enable i/o port control registers each i/o port has its own control register known as p ac, to control the input/output confguration. with this control register , each cm os output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however , it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 i/o port a bit 7 ~ bit 0 input/output control 0: output 1: input
rev. 1.30 5? ???i? ??? ?01? rev. 1.30 53 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom pin-remapping functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by suppl ying pi ns wi th m ulti-functions, m any of t hese di fficulties c an be ove rcome. t he wa y i n which the pin function of each pin is selected is dif ferent for each function and a priority order is established whe re m ore t han one pi n func tion i s se lected si multaneously. addi tionally t here i s a prm register to establish certain pin functions. generally speaking, the analog function has higher priority than the digital function. pin-remapping registers the limited number of supplied pins in a package can i mpose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several dif ferent functions and providing a means of function selection, a wide range of dif ferent functions can be incorporated into even relatively small package sizes. prm register register name bit 7 6 5 4 3 2 1 0 name prms ? prms6 prms5 prms4 prms3 prms ? prms1 prms0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 prms7~prms6: tck1 pin-remapping function selection bit 00: tck1 on pa2 01: tck1 on pa7 10: undefned 11: tck1 on pa4 bit 5 prms5: tck0 pin-remapping function selection bit 0: tck0 on pa7 1: tck0 on pa6 bit 4 prms4: tp1_0 pin-remapping function selection bit 0: tp1_0 on pa6 1: tp1_0 on pa7 bit 3 prms3: tp0_1 pin-remapping function selection bit 0: tp0_1 on pa5 1: tp0_1 on pa1 bit 2 prms2: tp0_0 pin-remapping function selection bit 0: tp0_0 on pa2 1: tp0_0 on pa0 bit 1~0 prms1~prms0: int pin-remapping function selection bit 00: int on pa5 01: int on pa2 10: int on pa3 11: int on pa7
rev. 1.30 54 ??? i ? ??? ? 01 ? rev. 1.30 55 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.

??? ? ? ? ?? generic input/output structure

? ?
? ? ? ? - ? ? - ? ? ? ? a/d input/output structure
rev. 1.30 54 ???i? ??? ?01? rev. 1.30 55 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom programming considerations within the user program, one of the frst things to consider is port initi alisation. after a reset, all of the i/o data and port control register will be set high. this means that all i/o pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high selections have been chosen. if the port control register , p ac, is then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data register , p a, is frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "set [m].i" and "clr [m].i" instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. the power -on reset condition of the a/d converter control registers ensures that any a/d input pins whi ch a re a lways sha red wi th ot her i/ o func tions wi ll be se tup a s a nalog i nputs a fter a re set. although these pins will be confgured as a/d inputs after a reset, the a/d converter will not be switched on. it i s t herefore i mportant t o not e t hat i f i t i s re quired t o use t hese pi ns a s i/ o di gital input pins or as other functions, the a/d converter control registers must be correctly programmed to remove the a/d funct ion. note al so that as the a/d channe l is enabled, any inte rnal pul l-high resistor connections will be removed. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. t o implement time related functions each device includes several t imer modules, abbreviated t o t he na me t m. t he t ms a re m ulti-purpose t iming un its a nd se rve t o pr ovide operations such as t imer/counter, compare match output as well as being the functional unit for the ge neration of pw m si gnals. e ach of t he t ms ha s t wo i ndividual i nterrupts. t he a ddition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. introduction the devices contain tw o tm s w ith each tm having a reference name of tm 0 and tm 1. each individual tm can be categorised as a certain type, namely compact t ype tm, so called ctm. the main features of the tms are summarised in the accompanying table. function ctm time ? /counte ? com ? a ? e match out ? ut pwm channe ? s 1 pwm ?? ignment edge pwm ? djustment pe ? iod & duty duty o ? pe ? iod tm function summary
rev. 1.30 56 ??? i ? ??? ? 01 ? rev. 1.30 5? ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom tm operation these two t ms offer a range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. when the free running counter has the same value as the pre-programmed comparator , known as a compare match situation, a tm interrupt signal will be generated which can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the clock source which drives the main counter in each tm can originate from various sources. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f lirc clock source or the external tckn pin. note that setting these bits to the value 101 will select a reserved clock input, in ef fect disconnecting the tm clock source. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the compact type tms each have two internal interrupts, one for each of the internal comparator a or comparator p , which generate a tm interrupt when a compare match condition occurs. when a tm interrupt is generated it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tm s has one tm input pin, w ith the label tck n. the tm input pin, is es sentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register . this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functi ons but will be connected to the inte rnal tm if selected using the tnck2~tnck0 bits. the tm input pin can be chosen to have either a rising or falling active edge. the tms each have two output pins w ith the label tpn_0 and tpn_1. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn_0 and tpn_1 output pins are also the pins where the tm generates the pwm output waveform. as the tpn_0 and tpn_1 pins are pin-shared with other functions, the tpn_0 or tpn_1 pin function is enabled or disabled according to the internal tm on/of f control, operation mode and output control settings. when the corresponding tm confguration selects the tp n_0 or tp n_1 pin to be used as an output pin, the associated pin will be setup as an external tm output pin. if the tm confguration determines that the t pn_0 o r t pn_1 p in fu nction i s n ot u sed, t he a ssociated p in wi ll b e c ontrolled by o ther p in- shared functions. the details of the tpn_0 or tpn_1 pin for each tm and device are provided in the accompanying table. device tm0 tm1 HT66F005/ht66f006 tp0_0 ? tp0_1 tp1_0 ? tp1_1 tm output pins
rev. 1.30 56 ???i? ??? ?01? rev. 1.30 5 ? ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom

HT66F005/ht66f006 tm function pin control block diagram
rev. 1.30 58 ??? i ? ??? ? 01 ? rev. 1.30 59 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom tm input/output pin control registers selecting t o ha ve a t m i nput/output or whe ther t o re tain i ts ot her sha red func tion i s i mplemented using one register , with a single bit in each register corresponding to a tm input/output pin. setting the bit high will setup the corresponding pin as a tm input/output, if reset to zero the pin will retain its original other function. tmpc register bit 7 6 5 4 3 2 1 0 name t1cp1 t1cp0 t0cp1 t0cp0 r/w r/w r/w r/w r/w por 0 1 0 1 bit 7 ~ 4 unimplemented, read as "0" bit 3 t1cp1: tp1_1 pin control 0: disable 1: enable bit 2 t1cp0: tp1_0 pin control 0: disable 1: enable bit 1 t0cp1: tp0_1 pin control 0: disable 1: enable bit 0 t0cp0: tp0_0 pin control 0: disable 1: enable programming considerations the tm counter registers and the capture/compare ccra registers, being 10-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these registe r pairs must be carried out in a specifc way . the important point to note is that data transfer to and from the 8-bit buf fer and its related l ow b yte o nly t akes p lace wh en a wr ite o r r ead o peration t o i ts c orresponding h igh b yte i s executed. data bus 8- bit buffe? tmxdh tmxdl tmx?h tmx?l tm counte? registe? ( read on?y ) tm ccr? registe? ( read / w?ite )
rev. 1.30 58 ???i? ??? ?01? rev. 1.30 59 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom the following steps show the read and write procedures: ? writing data to ccra ? step 1. w rite data to low byte tmxal C note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte tmxah C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra ? step 1. read data from the high byte tmxdh, tmxah C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl, tmxal C this step reads data from the 8-bit buffer. as t he ccra re gister i s i mplemented i n t he wa y shown i n t he fol lowing di agram a nd a ccessing this register is carried out in a specifc way described above, it is recommended to use the mov instruction t o a ccess t he c cra l ow b yte r egister, n amed t mxal, i n t he f ollowing a ccess procedures. accessing the ccra low byte register without following these access procedures will result in unpredictable values. compact type tm C ctm the c ompact t m t ype c ontains t hree o perating m odes, wh ich a re c ompare ma tch ou tput, t imer/ event counter and pwm output modes. the compact tm can also be controlled with an external input pin and can drive two external output pins. ctm name tm no. tm input pin tm output pin HT66F005/ht66f006 10-bit ctm 0 ? 1 tck0 ? tck1 tp0_0 ? tp0_1 ? tp1_0 ? tp1_1
? ? ? ? ? ? ? ? ? ?
? ?
? ?

? ? ?
? - - ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? ? ?? ? ?? compact type tm block diagram (n=0, 1)
rev. 1.30 60 ??? i ? ??? ? 01 ? rev. 1.30 61 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom compact tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. t here a re a lso t wo i nternal c omparators wi th t he na mes, com parator a a nd com parator p. t hese c omparators wi ll c ompare t he v alue i n t he c ounter wi th c crp a nd c cra r egisters. t he ccrp is 3-bit w ide w hose value is compared w ith the highes t three bits in the counter w hile the ccra is 10-bit wide and therefore compares with all counter bits. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers. compact type tm register description overall operation of the compact tm is controlled using several registers. a read only register pair e xists t o st ore t he i nternal c ounter 10 -bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmpc t1cp1 t1cp0 t0cp1 t0cp0 tmnc0 tnp ? u tnck ? tnck1 tnck0 tnon tnrp ? tnrp1 tnrp0 tmnc1 tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr tmndl d ? d6 d5 d4 d3 d ? d1 d0 tmndh d9 d8 tmn ? l d ? d6 d5 d4 d3 d ? d1 d0 tmn ? h d9 d8 compact tm register list (n=0 or 1) tmndl register bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d3 d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tmndl: tmn counter low byte register bit 7~bit 0 tmn 10-bit counter bit 7~bit 0 tmndh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tmndh: tmn counter high byte register bit 1~bit 0 tmn 10-bit counter bit 9~bit 8
rev. 1.30 60 ???i? ??? ?01? rev. 1.30 61 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom tmnal register bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tmnal: tmn ccra low byte register bit 7~bit 0 tmn 10-bit ccra bit 7~bit 0 tmnah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tmnah: tmn ccra high byte register bit 1~bit 0 tmn 10-bit ccra bit 9~bit 8 tmnc0 register bit 7 6 5 4 3 2 1 0 name tnp ? u tnck ? tnck1 tnck0 tnon tnrp ? tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tnpau: tmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0: select tmn counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f lirc 101: undefned 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will ef fectively disable the internal counter . the external pin clock source can be chosen to be act ive on the rising or falli ng edge . the clock source f sys is the system clock, while f h and f lirc are other internal clocks, the details of which can be found in the oscillator section.
rev. 1.30 6 ? ??? i ? ??? ? 01 ? rev. 1.30 63 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom bit 3 tnon: tmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run, cle aring the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high. bit 2~0 tnrp2~tnrp0: tmn ccrp 3-bit register, compared with the tmn counter bit 9~bit 7 comparator p match period 000: 1024 tmn clocks 001: 128 tmn clocks 010: 256 tmn clocks 011: 384 tmn clocks 100: 512 tmn clocks 101: 640 tmn clocks 110: 768 tmn clocks 111: 896 tmn clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are then compared with the internal counter s highest three bits. the result of this comparison c an be se lected t o c lear t he i nternal c ounter i f t he t ncclr bi t i s se t t o zero. set ting t he t ncclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value.
rev. 1.30 6? ???i? ??? ?01? rev. 1.30 63 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom tmnc1 register bit 7 6 5 4 3 2 1 0 name tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t nm1~tnm0: select tm n operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the tnm1 and tnm0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 tnio1~tnio0: select tpn_0, tpn_1 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in t he com pare ma tch out put mode , t he t nio1 a nd t nio0 bi ts de termine how t he tm out put pin changes sta te when a compare ma tch occurs from the com parator a. the tm output pi n can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit in the tmnc1 register . note that the output level requested by the tnio1 and tnio0 bits must be dif ferent from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odified b y c hanging t hese t wo b its. i t i s n ecessary t o o nly c hange t he values of t he t nio1 a nd t nio0 bi ts onl y a fter t he t mn ha s be en swi tched of f. unpredictable pwm outputs will occur if the t nio1 and t nio0 bits are changed when the tm is running.
rev. 1.30 64 ??? i ? ??? ? 01 ? rev. 1.30 65 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom bit 3 tnoc: tp n _0, tp n _1 output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode. it has no effect if the tm is in the t imer/counter mode. in the compare match output mode it determines the logic level of he tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 tnpol: tpn_0, tpn_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn_0 or tpn_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the t imer/counter mode. bit 1 tndpx: tmn pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 tncclr: select tmn counter clear condition 0: tmn comparator p match 1: tmn comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he compact tm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm mode.
rev. 1.30 64 ???i? ??? ?01? rev. 1.30 65 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom compact type tm operating modes the compact t ype tm can operate in one of three operating modes, compare match output mode, pwm mo de o r t imer/counter mo de. t he o perating m ode i s se lected u sing t he t nm1 a nd t nm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow . here both tnaf and tnpf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the tnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag is ge nerated a fter a c ompare m atch oc curs from co mparator a. t he t npf i nterrupt re quest fl ag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he tnio1 and tnio0 bits in the tmnc1 register . the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
rev. 1.30 66 ??? i ? ??? ? 01 ? rev. 1.30 6? ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom counte? va?ue 0x3 ff ccrp ccr? tnon tnp?u tnpol ccrp int . f?ag tnpf ccr? int . f?ag tn?f tm o / p pin time ccrp =0 ccrp > 0 counte? ove?f?ow ccrp > 0 counte? c?ea?ed by ccrp va?ue pause resume sto? counte? resta?t tncclr = 0 ; tnm [1:0 ] = 00 out?ut ?in set to initia? leve? low if tnoc =0 out?ut togg?e with tn?f f?ag note tnio [1:0 ] = 10 ?ctive high out?ut se?ect he?e tnio [1:0 ] = 11 togg?e out?ut se?ect out?ut not affected by tn?f f?ag . remains high unti? ?eset by tnon bit out?ut pin reset to initia? va?ue out?ut cont?o??ed by othe? ?in - sha?ed function out?ut inve?ts when tnpol is high compare match output mode C tncclr=0 note: 1. w ith tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge
rev. 1.30 66 ???i? ??? ?01? rev. 1.30 6 ? ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom counte? va?ue 0x3ff ccrp ccr? tnon tnp?u tnpol ccrp int. f?ag tnpf ccr? int. f?ag tn?f tm o/p pin time ccr?=0 ccr? = 0 counte? ove?f?ow ccr? > 0 counte? c?ea?ed by ccr? va?ue pause resume sto? counte? resta?t tncclr = 1; tnm [1:0] = 00 out?ut ?in set to initia? leve? low if tnoc=0 out?ut togg?e with tn?f f?ag note tnio [1:0] = 10 ?ctive high out?ut se?ect he?e tnio [1:0] = 11 togg?e out?ut se?ect out?ut not affected by tn?f f?ag. remains high unti? ?eset by tnon bit out?ut pin reset to initia? va?ue out?ut cont?o??ed by othe? ?in-sha?ed function out?ut inve?ts when tnpol is high tnpf not gene?ated no tn?f f?ag gene?ated on ccr? ove?f?ow out?ut does not change compare match output mode C tncclr=1 note: 1. w ith tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1
rev. 1.30 68 ??? i ? ??? ? 01 ? rev. 1.30 69 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively . the pwm functio n within the tm is useful for applications which require functions such as motor control, h eating c ontrol, i llumination c ontrol e tc. b y p roviding a si gnal o f f ixed f requency b ut of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pwm m ode, t he t ncclr bi t ha s no e ffect on t he pwm operation. bot h of t he ccra a nd ccrp re gisters a re use d t o ge nerate t he pw m wave form, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register . the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ctm, pwm mode, edge-aligned mode, tndpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod 1 ? 8 ? 56 384 51 ? 640 ? 68 896 10 ? 4 duty ccr ? if f sys =16mhz, tm clock source is f sys /4, ccrp=100b and ccra=128, the ctm pwm output frequency=(f sys /4)/512=f sys /2048=7.8125 khz, duty=128/512=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ctm, pwm mode, edge-aligned mode, tndpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod ccr ? duty 1 ? 8 ? 56 384 51 ? 640 ? 68 896 10 ? 4 the pw m o utput p eriod i s d etermined b y t he c cra r egister v alue t ogether wi th t he t m c lock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.30 68 ???i? ??? ?01? rev. 1.30 69 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom counte? va?ue ccrp ccr? tnon tnp?u tnpol ccrp int. f?ag tnpf ccr? int. f?ag tn?f tm o/p pin (tnoc=1) time counte? c?ea?ed by ccrp pause resume counte? sto? if tnon bit ?ow counte? reset when tnon ?etu?ns high tndpx = 0; tnm [1:0] = 10 pwm duty cyc?e set by ccr? pwm ?esumes o?e?ation out?ut cont?o??ed by othe? ?in-sha?ed function out?ut inve?ts when tnpol = 1 pwm pe?iod set by ccrp tm o/p pin (tnoc=0) pwm mode C tndpx=0 note: 1. here tndpx=0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.30 ? 0 ??? i ? ??? ? 01 ? rev. 1.30 ?1 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom counte? va?ue ccrp ccr? tnon tnp?u tnpol ccrp int. f?ag tnpf ccr? int. f?ag tn?f tm o/p pin (tnoc=1) time counte? c?ea?ed by ccr? pause resume counte? sto? if tnon bit ?ow counte? reset when tnon ?etu?ns high tndpx = 1; tnm [1:0] = 10 pwm duty cyc?e set by ccrp pwm ?esumes o?e?ation out?ut cont?o??ed by othe? ?in-sha?ed function out?ut inve?ts when tnpol = 1 pwm pe?iod set by ccr? tm o/p pin (tnoc=0) pwm mode C tndpx=1 note: 1. here tndpx=1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.30 ?0 ???i? ??? ?01? rev. 1.30 ? 1 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the devices contain a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. part no. input channels a/d channel select bits input pins HT66F005/ht66f006 4 ? cs4 ? ? cs1~ ? cs0 ? n0~ ? n3 the accompanying block diagram shows the overall internal structure of the a/d converter , together with its associated registers.
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? ?? ? ? ? ? ? ? ? ??? ? a/d converter structure a/d converter register description overall operation of the a /d converter is controlled us ing f ve regis ters. a read only regis ter pair exists to store the adc data 12-bit value. the remaining three register s are control registers which setup the operating and control function of the a/d converter. register name bit 7 6 5 4 3 2 1 0 ? drl( ? drfs=0) d3 d ? d1 d0 ? drl( ? drfs=1) d ? d6 d5 d4 d3 d ? d1 d0 ? drh( ? drfs=0) d11 d10 d9 d8 d ? d6 d5 d4 ? drh( ? drfs=1) d11 d10 d9 d8 ? dcr0 st ? rt eocb ? doff ? drfs ? cs1 ? cs0 ? dcr1 ? cs4 v1 ? 5en vrefs ? dck ? ? dck1 ? dck0 ? cer ? ce3 ? ce ? ? ce1 ? ce0 a/d converter register list
rev. 1.30 ?? ??? i ? ??? ? 01 ? rev. 1.30 ?3 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom a/d converter data registers C adrl, adrh as the devices contain an internal 12-bit a/d converter , they require two data registers to store the converted va lue. t hese a re a hi gh byt e re gister, kno wn a s adr h, a nd a l ow byt e re gister, kno wn as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the adrfs bit in the adcr0 register as shown in the accompany ing table. d0~d1 1 are the a/d conversion result data bits. any unused bits will be read as zero. adrfs adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d ? d6 d5 d4 d3 d ? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d ? d6 d5 d4 d3 d ? d1 d0 a/d data registers a/d converter control registers C adcr0, adcr1, acer to control the function and operation of the a/d converter, three control registers known as adcr0, adcr1 and a cer are provided. thes e 8-bit regis ters define functions s uch as the s election of which analog channel is connected to the internal a /d converter , the digitis ed data format, the a / d clock source as well as controlling the start function and monitoring the a/d converter end of conversion status. the acs1~acs0 bits in the adcr0 register and acs4 bit is the adcr1 register define the adc input channel number . as the device contains only one actual analog to digital converter hardware circuit, each of the individual 4 analog inputs must be routed to the converter . it is the function of the acs4 and acs1~acs0 bits to determine which analog channel input pins or internal 1.25v is actually connected to the internal a/d converter. the acer control register contains the ace3~ace0 bits which determ ine which pins on p a0~pa3 are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. setting the corresponding bit high will select the a/d input function, clearing the bit to zero will select either the i/o or other pin-shared function. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be removed. in addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input.
rev. 1.30 ?? ???i? ??? ?01? rev. 1.30 ? 3 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom adcr0 register bit 7 6 5 4 3 2 1 0 name st ? rt eocb ? doff ? drfs ? cs1 ? cs0 r/w r/w r r/w r/w r/w r/w por 0 1 1 0 0 0 bit 7 start: start the a/d conversion 010: start 01: reset the a/d converter and set eocb to 1 this bit is used to initiate an a/ d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb: end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running, the bit will be high. bit 5 adoff : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter . if the bit is set high then the a/d converter will be switched of f reducing the device power consumption. as the a/d converter will consume a limited amount of power , even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. bit 4 adrfs: adc data format control 0: adc data msb is adrh bit 7, lsb is adrl bit 4 1: adc data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3~2 unimplemented, read as 0 bit 1~0 acs2, acs1, acs0: select a/d channel (when acs4 is 0) 000: an0 001: an1 010: an2 011: an3
rev. 1.30 ? 4 ??? i ? ??? ? 01 ? rev. 1.30 ?5 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom adcr1 register bit 7 6 5 4 3 2 1 0 name ? cs4 v1 ? 5en vrefs ? dck ? ? dck1 ? dck0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 acs4: select internal 1.25v bandgap voltage as adc input 0: disable 1: enable this bit enables the1.25v bandgap voltage to be connected to the a/d converter . the v125en bit must frst have been set to enable the bandgap circuit 1.25v voltage to be used by the a/d converter . when the acs4 bit is set high, the bandgap 1.25v voltage will be routed to the a/d converter and the other a/d input channels disconnected. bit 6 v125en: internal 1.25v control 0: disable 1: enable this bit controls the internal bandgap circuit on/of f function to the a/d converter . when the bit is set high the bandgap voltage 1.25v can be used as an a/d converter input. if the bandgap voltage 1.25v is not used by the a/d converter and the lvr/lvd function is disable d then the bandgap reference circuit will be automatically switched off to conserve power. when 1.25v is switched on for use by the a/d converter, a time t bg should be allowed for the bandgap circuit to stabilise before implementing an a/d conversion. bit 5 unimplemented, read as "0" bit 4 vrefs: select adc reference voltage 0: internal adc power 1: vref pin this bit is used to select the reference voltage for the a/d converter . if the bit is high, then the a/d converter reference voltage is supplied on the external vref pin. if the pin is low, then the internal reference is used which is taken from the power supply pin vdd. bit 3 unimplemented, read as "0" bit 2~0 adck2, adck1, adck0: select adc clock source 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: undefned these three bits are used to select the clock source for the a/d converter.
rev. 1.30 ?4 ???i? ??? ?01? rev. 1.30 ? 5 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom acer register bit 7 6 5 4 3 2 1 0 name ? ce3 ? ce ? ? ce1 ? ce0 r/w r/w r/w r/w r/w por 1 1 1 1 bit 7~4 unimplemented, read as "0" bit 3 ace3: defne pa3 is a/d input or not 0: not a/d input 1: a/d input, an3 bit 2 ace2: defne pa2 is a/d input or not 0: not a/d input 1: a/d input, an2 bit 1 ace1: defne pa1 is a/d input or not 0: not a/d input 1: a/d input, an1 bit 0 ace0: defne pa0 is a/d input or not 0: not a/d input 1: a/d input, an0 a/d operation the st art bi t i n t he adcr0 re gister i s use d t o st art a nd re set t he a/ d c onverter. w hen t he microcontroller s ets this bit from low to high and then low again, an analog to digital convers ion cycle will be initiated. when the st art bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. it is the st art bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bi t i n t he adcr0 regi ster i s use d t o i ndicate when t he ana log t o di gital conve rsion process is comple te. this bit will be automatically set to 0 by the micro controller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register , and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter , which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the adck2~adck0 bits in the adcr1 register. although the a/ d clock source is determined by the system clock f sys , and by bits adck2~adck0, there are some limitations on the a/d clock source speed range that can be selected. as the recommended range of permissible a/d clock period, t adck , is from 0.5s to 10s, care must be taken for selected system clock frequencies. for example, if the system clock operates at a frequency of 4mhz, the adck2~adck0 bits should not be set to 000b or 1 10b. doing so will give a/d clock p eriods t hat a re l ess t han t he m inimum a/ d c lock p eriod o r g reater t han t he m aximum a/ d clock period which may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period.
rev. 1.30 ? 6 ??? i ? ??? ? 01 ? rev. 1.30 ?? ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom f sys a/d clock period (t adck ) adck2, adck1, adck0 =000 (f sys ) adck2, adck1, adck0 =001 (f sys /2) adck2, adck1, adck0 =010 (f sys /4) adck2, adck1, adck0 =011 (f sys /8) adck2, adck1, adck0 =100 (f sys /16) adck2, adck1, adck0 =101 (f sys /32) adck2, adck1, adck0 =110 (f sys /64) adck2, adck1, adck0 =111 1mhz 1s 2s 4s 8s 16s* 32s* 64s* undefned ? mhz 500ns 1s 2s 4s 8s 16s* 32s* undefned 4mhz ? 50ns* 500ns 1s 2s 4s 8s 16s* undefned 8mhz 1 ? 5ns* ? 50ns* 500ns 1s 2s 4s 8s undefned 1 ? mhz 83ns* 16 ? ns* 333ns* 66 ? ns 1.33s 2.67s 5.33s undefned a/d clock period examples controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he adoff bit in the adcr0 register . this bit must be zero to power on the a/d converter . when the adoff bit is cleared to zero to power on the a/d converter internal circuitry a certain delay , as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs by clearing the ace3~ace0 bits in the acer register , if the adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, vdd, or from an external reference sources supplied on pin vref . the desired selection is made using the vrefs bit. as the vref pin is pin-shared with other functions, when the vrefs bit is set high, the vref pin function will be selected and the other pin functions will be disabled automatically. a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins on p a3~pa0 as well as other functions. the ace3~ ace0 bits in the acer register determines whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the ace3~ ace0 bits for its corresponding pin is set high then the pin will be setup to be an a/d converter input and the original pin functions disabled. in this way , pins can be changed under program control to change their function bet ween a/ d input s and othe r func tions. al l pull -high resi stors, whi ch are se tup through register programm ing, will be autom atically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the p ac port control register to enable the a/d input as when the ace3~ ace0 bits enable an a/d input, the status of the port control register will be overridden. the a/d converter has its own reference voltage pin vref however the reference voltage can also be supplied from the power supply pin, a choice which is made through the vrefs bit in the adcr1 register. the analog input values must not be allowed to exceed the value of vref .
rev. 1.30 ?6 ???i? ??? ?01? rev. 1.30 ?? ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom
? ? ? ? ?? ? ? - a/d input structure summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. ? step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. ? step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs4, acs1~acs0 bits which are also contained in the adcr1 and adcr0 register. ? step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the ace3~ace0 bits in the acer register. ? step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master inter rupt control bit, emi, and the a/d converter interrupt bit, ade, must both be set high to do this. ? step 6 the analog to digital conversion process can now be initialised by setting the st art bit in the adcr0 register from low to high and then low again. note that this bit should have been originally cleared to 0. ? step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register ca n be poll ed. the conversion proc ess is com plete when t his bit goes l ow. when thi s occurs the a/d data register adrl and adrh can be read to obtain the conversion value. as an alternative method , if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware w ill begin to carry out the conversion, d uring wh ich t ime t he p rogram c an c ontinue wi th o ther f unctions. t he t ime t aken f or t he a/d conversion is 16t adck where t adck is equal to the a/d clock period.
rev. 1.30 ? 8 ??? i ? ??? ? 01 ? rev. 1.30 ?9 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom

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? ? ? - ? ? ? ? ?? - a/d conversion timing programming considerations during microcontroller operates where the a/d converter is not being used, the a/d internal circuitry can be switched of f to reduce power consumption, by setting bit adoff high in the adcr0 r egister. w hen t his h appens, t he i nternal a/ d c onverter c ircuits wi ll n ot c onsume p ower irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. the power -on rese t condi tion of t he a/ d convert er cont rol regi sters wi ll ensure t hat t he sha red function pins are setup as a/d converter inputs. if any of the a/d converter input pins are to be used for other functions, then the a/d converter control register bits must be properly setup to disable the a/d input confguration. a/d transfer function as the devices contain a 12-bit a/d converter , its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb=(v dd or v ref )4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage=a/d output digital value (v dd or v ref )4096 the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd or v ref level.
rev. 1.30 ?8 ???i? ??? ?01? rev. 1.30 ? 9 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom

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? ideal a/d transfer function a/d programming examples the following two programming examples illustrate how to setup and implement an a/d conversion. in t he fr st e xample, t he m ethod o f p olling t he e ocb b it i n t he adc r0 r egister i s u sed t o d etect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example 1: using an eocb polling method to detect the end of conversion clr a de ; disable adc interrupt mov a,03h mov adcr1,a ; s elect f sys /8 as a /d c lock a nd s witch o ff 1 .25v clr adoff mov a,0fh ; s etup a cer t o c onfgure p ins a n0~an3 mov acer,a mov a,00h mov adcr0,a ; e nable an d c onnect a n0 c hannel t o a /d c onverter : start_conversion: clr st art ; h igh p ulse o n s tart b it t o i nitiate c onversion set s tart ; r eset a /d clr s tart ; s tart a /d polling_eoc: sz e ocb ; p oll t he a dcr0 r egister e ocb b it t o d etect e nd ; o f a /d c onversion jmp p olling_eoc ; c ontinue p olling mov a ,adrl ; re ad l ow b yte c onversion re sult v alue mov a drl_buffer,a ; s ave r esult t o us er d efned r egister mov a ,adrh ; re ad h igh b yte c onversion re sult v alue mov a drh_buffer,a ; s ave r esult t o us er d efned r egister : : jmp start_conversion ; st art n ext a/d c onversion
rev. 1.30 80 ??? i ? ??? ? 01 ? rev. 1.30 81 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom example 2: using the interrupt method to detect the end of conversion clr a de ; disable adc interrupt mov a,03h mov adcr1,a ; s elect f sys /8 as a /d c lock a nd s witch o ff 1 .25v clr adoff mov a,0fh ; s etup a cer t o c onfgure p ins a n0~an3 mov acer,a mov a,00h mov adcr0,a ; e nable an d c onnect a n0 c hannel t o a /d c onverter start_conversion: clr st art ; h igh p ulse o n st art b it t o i nitiate c onversion set s tart ; r eset a /d clr s tart ; s tart a /d clr a df ; c lear a dc i nterrupt re quest f ag s et ade ; enable adc interrupt set e mi ; e nable gl obal i nterrupt : : ; adc interrupt service routine adc_isr: mov ac c_stack,a ; s ave a cc t o u ser d efned m emory mov a ,status mov s tatus_stack,a ; s ave st atus t o us er d efned m emory : : mov a ,adrl ; re ad l ow b yte c onversion re sult v alue mov a drl_buffer,a ; s ave r esult t o us er d efned r egister mov a ,adrh ; re ad h igh b yte c onversion re sult v alue mov a drh_buffer,a ; s ave r esult t o us er d efned r egister : : exit_int_isr: mov a ,status_stack mov s tatus,a ; restore s tatus f rom u ser d efned m emory mov a ,acc_stack ; r estore a cc fr om u ser d efned m emory reti
rev. 1.30 80 ???i? ??? ?01? rev. 1.30 81 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains an external interrupt and internal interrupts functions. the external interrupt is generated by the action of the external int pin, while the internal interrup ts are generated by various interna l functions such as the tms, time base, eeprom and the a/d converter. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the special purpose data memory , as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. t he frst i s t he int c0~intc1 re gisters whi ch se tup t he pri mary i nterrupts, t he se cond is the mfi0~mfi1 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each register contains a number of enable bits to enable or disable individual interrupts as well as i nterrupt fa gs t o i ndicate t he p resence o f a n i nterrupt r equest. t he n aming c onvention o f t hese follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes g ? oba ? emi int pin inte intf mu ? ti-function mfne mfnf n=0~1 ? /d conve ? te ? ? de ? df time base tbne tbnf n=0~1 eeprom dee def tm tnpe tnpf n=0~1 tn ? e tn ? f interrupt register bit naming conventions interrupt register list stop here 19/12 name bit 7 6 5 4 3 2 1 0 integ ints1 ints0 intc0 mf0f tb0f intf mf0e tb0e inte emi intc1 tb1f ? de def mf1f tb1e ? de dee mf1e mfi0 t0 ? f t0pf t0 ? e t0pe mfi1 t1 ? f t1pf t1 ? e t1pe
rev. 1.30 8 ? ??? i ? ??? ? 01 ? rev. 1.30 83 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom integ register bit 7 6 5 4 3 2 1 0 name ints1 ints0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0 bit 1~0 int0s1~int0s0: interrupt edge control for int pin 00: disable 01: rising edge 10: falling edge 11: both rising and falling edges intc0 register bit 7 6 5 4 3 2 1 0 name mf0f tb0f intf mf0e tb0e inte emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 mf0f: multi-function 0 interrupt request fag 0: no request 1: interrupt request bit 5 tb0f: t ime base 0 interrupt request fag 0: no request 1: interrupt request bit 4 intf: int interrupt request fag 0: no request 1: interrupt request bit 3 mf0e: multi-function 0 interrupt control 0: disable 1: enable bit 2 tb0e: t ime base 0 interrupt control 0: disable 1: enable bit 1 inte: int interrupt control 0: disable 1: enable bit 0 emi: global interrupt control 0: disable 1: enable
rev. 1.30 8? ???i? ??? ?01? rev. 1.30 83 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom intc1 register bit 7 6 5 4 3 2 1 0 name tb1f ? df def mf1f tb1e ? de dee mf1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tb1f: time base 1 interrupt request fag 0: no request 1: interrupt request bit 6 adf: a/d converter interrupt request fag 0: no request 1: interrupt request bit 5 def: data eeprom interrupt request fag 0: no request 1: interrupt request bit 4 mf1f: multi-function 1 interrupt request fag 0: no request 1: interrupt request bit 3 tb1e: t ime base 1 interrupt control 0: disable 1: enable bit 2 ade: a/d converter interrupt control 0: disable 1: enable bit 1 dee: data eeprom interrupt control 0: disable 1: enable bit 0 mf1e: multi-function 1 interrupt control 0: disable 1: enable
rev. 1.30 84 ??? i ? ??? ? 01 ? rev. 1.30 85 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom mfi0 register bit 7 6 5 4 3 2 1 0 name t0 ? f t0pf t0 ? e t0pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 t0af: tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf: tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 t0ae: tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe: tm0 comparator p match interrupt control 0: disable 1: enable mfi1 register bit 7 6 5 4 3 2 1 0 name t1 ? f t1pf t1 ? e t1pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 t1af: tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf: tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 t1ae: tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe: tm1 comparator p match interrupt control 0: disable 1: enable
rev. 1.30 84 ???i? ??? ?01? rev. 1.30 85 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom interrupt operation when the conditions for an interrupt event occur , such as a tm comparator p or comparator a match or a/d conversion completion, etc., the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enabl e bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated w ith a reti, w hich retrieves the original p rogram counter address from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . o nce an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. al l o f t he i nterrupt r equest fa gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode.
rev. 1.30 86 ??? i ? ??? ? 01 ? rev. 1.30 8? ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom 04h 08h 0ch 10h 14h 18h vector low p ? io ? ity high request f ? ags enab ? e bits maste ? enab ? e request f ? ags enab ? e bits emi auto disab ? ed in isr inte ?? u? ts contained within mu? ti - function inte ?? u? ts inte ?? u?t name inte ?? u?t name emi emi emi emi emi t1 ?f tm1 ? t1 ?e t1pf tm1 p t1pe intf int pin inte tb0f time base 0 tb0e mf0f m. funct . 0 mf0e mf1f m. funct . 1 mf1e ? df ? /d ? de emi def eeprom dee xxf legend request f ? ag C no auto ? eset in isr xxf request f ? ag C auto ? eset in isr xxe enab ? e bit t0 ?f tm0 ? t0pf tm0 p t0 ?e t0pe 1ch emi tb1f time base 1 tb1e interrupt structure
rev. 1.30 86 ???i? ??? ?01? rev. 1.30 8 ? ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom external interrupt the external interrupt is controlled by signal transitions on the int pin. an external interrupt request will take place when the external interrupt request fag, intf , is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and res pective external interrupt enable bit, in te, mus t f rst be s et. a dditionally the correct interrupt edge type mus t be s elected us ing the in teg regis ter to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pin is pin-shared with an i/ o pin, it can only be confgured as an external interrupt pin if its external interrupt enable bit in the corresponding inte rrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register . when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the external interrupt request fags, intf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selection on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. multi-function interrupt within these devices there are two multi-function interrupts. unlike the other independent interrupts, these int errupts have no i ndependent sourc e, but rat her are form ed from other exi sting i nterrupt sources, namely the tm interrupts. a multi-function interrupt request will take place when any of the multi-function interrupt request flags, mfnf are set. the multi-function interrupt flags will be set when any of their included functions generate an interrupt request fag. t o allow the program to branch to its respective interrupt vector address, when the multi-func tion interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi- function request fag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, i t m ust be not ed t hat, a lthough t he mul ti-function int errupt fa gs wi ll be a utomatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, namely the tm interrupt s, will not be automatically reset and must be manually reset by the application program. a/d converter interrupt the devices conta in an a/d converter which has its own independent interrupt. the a/d converter interrupt is controlled by the termin ation of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf , is set, which occurs when the a/d conversion process fnishes. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and a/d interrupt enable bit, ade, must frst be set. when the inte rrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converte r interrupt vector , will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts.
rev. 1.30 88 ??? i ? ??? ? 01 ? rev. 1.30 89 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom time base interrupts the function of the t ime base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the t ime base overfow s, a subroutine call to their res pective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the t ime base interrupt period, can originate from several dif ferent sources, as shown in the system operating mode section. tbc register bit 7 6 5 4 3 2 1 0 name tbon tbck tb11 tb10 tb0 ? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 1 1 1 bit 7 tbon: tb0 and tb1 control 0: disable 1: enable bit 6 tbck: select f tb clock 0: f tbc 1: f sys /4 bit 5~4 tb11~tb10: select t ime base 1 t ime-out period 00: 4096/f tb 01: 8192/f tb 10: 16384/f tb 11: 32768/f tb bit 3 unimplemented, read as "0" bit 2~0 tb02~tb00: select t ime base 0 t ime-out period 000: 256/f tb 001: 512/f tb 010: 1024/f tb 011: 2048/f tb 100: 4096/f tb 101: 8192/f tb 110: 16384/f tb 111: 32768/f tb

time base interrupts
rev. 1.30 88 ???i? ??? ?01? rev. 1.30 89 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom eeprom interrupt an eeprom interrupt request will take place when the eeprom interrupt request fag, def, is set, which occurs when an eeprom w rite cycle ends. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and eeprom interrupt enable bit, dee, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom w rite cycle ends, a subroutine call to the respective eeprom interrupt vect or, will take place. when the eeprom interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, and the eeprom interrupt request fag, def, will be also automatically cleared. tm interrupts the compact t ype tms have two interrupts each. all of the tm interrupts are contained within the multi-function interrupts. for each of the compact t ype tms there are two interrupt request fags tnpf and tnaf and two enable bits tnpe and tnae. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p or a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. interrupt wake-up function each of the int errupt funct ions has the capa bility of waki ng up the mi crocontroller when in the sleep o r i dle mo de. a wa ke-up i s g enerated wh en a n i nterrupt r equest fa g c hanges f rom l ow to high and is independent of whether the interrupt is enabled or not. therefore, even though these devices are in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pin, a low power supply voltage or comparator input change may cause their respective interrupt fl ag to be set hi gh and consequently generate an i nterrupt. c are m ust t herefore b e t aken i f sp urious wa ke-up si tuations a re t o b e a voided. i f a n interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interr upt enable bits have no ef fect on the interrupt wake-up function.
rev. 1.30 90 ??? i ? ??? ? 01 ? rev. 1.30 91 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service routine is executed, as only the multi-function interrupt request flags, mfnf , will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in the sleep or idle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.30 90 ???i? ??? ?01? rev. 1.30 91 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom confguration options confguration options refer to certa in options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht -ide software development tools. as these options are programmed into the device using the hardwa re programm ing tools, once they are sel ected they cannot be changed la ter using the application program. all options must be defned for proper system function, the details of which are shown in the table. no. options oscillator option 1 high s ? eed / low s ? eed system osci ?? ato ? se ? ection C f osc : hirc+lirc ? hxt+lirc watchdog option ? watchdog time ? : enab ? e/disab ? e ?? ways enab ? e d softwa ? e cont ? o ? ? ed application circuits

rev. 1.30 9 ? ??? i ? ??? ? 01 ? rev. 1.30 93 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.30 9? ???i? ??? ?01? rev. 1.30 93 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been c arried out. t his i s done by pl acing a re turn i nstruction ret i n t he subrout ine whi ch wi ll cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. de pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. however , whe n worki ng wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the hal t instruction for power -down operations and instructions to control the operation of the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.30 94 ??? i ? ??? ? 01 ? rev. 1.30 95 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic ? dd ?? [m] ? dd data memo ? y to ? cc 1 z ? c ? ? c ? ov ? ddm ?? [m] ? dd ? cc to data memo ? y 1 note z ? c ? ? c ? ov ? dd ?? x ? dd immediate data to ? cc 1 z ? c ? ? c ? ov ? dc ?? [m] ? dd data memo ? y to ? cc with ca ?? y 1 z ? c ? ? c ? ov ? dcm ?? [m] ? dd ? cc to data memo ? y with ca ?? y 1 note z ? c ? ? c ? ov sub ?? x subt ? act immediate data f ? om the ? cc 1 z ? c ? ? c ? ov sub ?? [m] subt ? act data memo ? y f ? om ? cc 1 z ? c ? ? c ? ov subm ?? [m] subt ? act data memo ? y f ? om ? cc with ? esu ? t in data memo ? y 1 note z ? c ? ? c ? ov sbc ?? [m] subt ? act data memo ? y f ? om ? cc with ca ?? y 1 z ? c ? ? c ? ov sbcm ?? [m] subt ? act data memo ? y f ? om ? cc with ca ?? y ? ? esu ? t in data memo ? y 1 note z ? c ? ? c ? ov d ?? [m] decima ? adjust ? cc fo ? ? ddition with ? esu ? t in data memo ? y 1 note c logic operation ? nd ?? [m] logica ? ? nd data memo ? y to ? cc 1 z or ?? [m] logica ? or data memo ? y to ? cc 1 z xor ?? [m] logica ? xor data memo ? y to ? cc 1 z ? ndm ?? [m] logica ? ? nd ? cc to data memo ? y 1 note z orm ?? [m] logica ? or ? cc to data memo ? y 1 note z xorm ?? [m] logica ? xor ? cc to data memo ? y 1 note z ? nd ?? x logica ? ? nd immediate data to ? cc 1 z or ?? x logica ? or immediate data to ? cc 1 z xor ?? x logica ? xor immediate data to ? cc 1 z cpl [m] com ?? ement data memo ? y 1 note z cpl ? [m] com ?? ement data memo ? y with ? esu ? t in ? cc 1 z increment & decrement inc ? [m] inc ? ement data memo ? y with ? esu ? t in ? cc 1 z inc [m] inc ? ement data memo ? y 1 note z dec ? [m] dec ? ement data memo ? y with ? esu ? t in ? cc 1 z dec [m] dec ? ement data memo ? y 1 note z rotate rr ? [m] rotate data memo ? y ? ight with ? esu ? t in ? cc 1 none rr [m] rotate data memo ? y ? ight 1 note none rrc ? [m] rotate data memo ? y ? ight th ? ough ca ?? y with ? esu ? t in ? cc 1 c rrc [m] rotate data memo ? y ? ight th ? ough ca ?? y 1 note c rl ? [m] rotate data memo ? y ? eft with ? esu ? t in ? cc 1 none rl [m] rotate data memo ? y ? eft 1 note none rlc ? [m] rotate data memo ? y ? eft th ? ough ca ?? y with ? esu ? t in ? cc 1 c rlc [m] rotate data memo ? y ? eft th ? ough ca ?? y 1 note c
rev. 1.30 94 ???i? ??? ?01? rev. 1.30 95 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom mnemonic description cycles flag affected data move mov ?? [m] move data memo ? y to ? cc 1 none mov [m] ?? move ? cc to data memo ? y 1 note none mov ?? x move immediate data to ? cc 1 none bit operation clr [m].i c ? ea ? bit of data memo ? y 1 note none set [m].i set bit of data memo ? y 1 note none branch operation jmp add ? jum ? unconditiona ?? y ? none sz [m] ski ? if data memo ? y is ze ? o 1 note none sz ? [m] ski ? if data memo ? y is ze ? o with data movement to ? cc 1 note none sz [m].i ski ? if bit i of data memo ? y is ze ? o 1 note none snz [m].i ski ? if bit i of data memo ? y is not ze ? o 1 note none siz [m] ski ? if inc ? ement data memo ? y is ze ? o 1 note none sdz [m] ski ? if dec ? ement data memo ? y is ze ? o 1 note none siz ? [m] ski ? if inc ? ement data memo ? y is ze ? o with ? esu ? t in ? cc 1 note none sdz ? [m] ski ? if dec ? ement data memo ? y is ze ? o with ? esu ? t in ? cc 1 note none c ? ll add ? sub ? outine ca ?? ? none ret retu ? n f ? om sub ? outine ? none ret ?? x retu ? n f ? om sub ? outine and ? oad immediate data to ? cc ? none reti retu ? n f ? om inte ?? u ? t ? none table read operation t ? brd [m] read table (specifc page) to tblh and data memory ? note none t ? brdc [m] read tab ? e (cu ?? ent ? age) to tblh and data memo ? y ? note none t ? brdl [m] read tab ? e ( ? ast ? age) to tblh and data memo ? y ? note none miscellaneous nop no o ? e ? ation 1 none clr [m] c ? ea ? data memo ? y 1 note none set [m] set data memo ? y 1 note none clr wdt c ? ea ? watchdog time ? 1 to ? pdf clr wdt1 p ? e-c ? ea ? watchdog time ? 1 to ? pdf clr wdt ? p ? e-c ? ea ? watchdog time ? 1 to ? pdf sw ? p [m] swa ? nibb ? es of data memo ? y 1 note none sw ? p ? [m] swa ? nibb ? es of data memo ? y with ? esu ? t in ? cc 1 none h ? lt ente ? ? owe ? down mode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the t o and pdf flags may be af fected by the execution sta tus. t he t o a nd pdf fl ags a re c leared a fter bot h clr w dt1 a nd clr w dt2 instructions are consecutively executed. otherwise the t o and pdf fags remain unchanged.
rev. 1.30 96 ??? i ? ??? ? 01 ? rev. 1.30 9? ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z
rev. 1.30 96 ???i? ??? ?01? rev. 1.30 9 ? ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt1 pre-clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re a ll c leared. n ote t hat t his instruction w orks in conjunction w ith c lr w dt2 a nd m ust b e e xecuted al ternately w ith c lr w dt2 to h ave effect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt2 w ill have no e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt2 pre-clear w atchdog t imer description the t o, p df f ags and t he w dt are all cleared. n ote t hat t his i nstruction w orks i n conjunction with c lr w dt1 a nd m ust b e e xecuted al ternately w ith c lr w dt1 to h ave e ffect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt1 w ill h ave n o e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z
rev. 1.30 98 ??? i ? ??? ? 01 ? rev. 1.30 99 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 1.30 98 ???i? ??? ?01? rev. 1.30 99 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none
rev. 1.30 100 ??? i ? ??? ? 01 ? rev. 1.30 101 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none
rev. 1.30 100 ???i? ??? ?01? rev. 1.30 101 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none
rev. 1.30 10 ? ??? i ? ??? ? 01 ? rev. 1.30 103 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c
rev. 1.30 10? ???i? ??? ?01? rev. 1.30 103 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none
rev. 1.30 104 ??? i ? ??? ? 01 ? rev. 1.30 105 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom tabrd [m] read ta ble ( specifc p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( specifc p age) a ddressed b y t he t able p ointer p air (tbhp a nd t blp) i s mo ved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdc [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 1.30 104 ???i? ??? ?01? rev. 1.30 105 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to pa ckaging is listed below. click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product t ape and reel specifcations) ? packing meterials information ? carton information
rev. 1.30 106 ??? i ? ??? ? 01 ? rev. 1.30 10? ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom 8-pin dip (300mil) outline dimensions symbol dimensions in inch min. nom. max. ? 0.355 0.365 0.400 b 0. ? 40 0. ? 50 0. ? 80 c 0.115 0.130 0.195 d 0.115 0.130 0.150 e 0.014 0.018 0.0 ?? f 0.045 0.060 0.0 ? 0 g 0.100 bsc h 0.300 0.310 0.3 ? 5 i 0.430 symbol dimensions in mm min. nom. max. ? 9.0 ? 9. ?? 10.16 b 6.10 6.35 ? .11 c ? .9 ? 3.30 4.95 d ? .9 ? 3.30 3.81 e 0.36 0.46 0.56 f 1.14 1.5 ? 1. ? 8 g ? .54 bsc h ? . ? 6 ? .8 ? 8. ? 6 i 10.9 ?
rev. 1.30 106 ???i? ??? ?01? rev. 1.30 10 ? ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom 8-pin sop (150mil) outline dimensions symbol dimensions in inch min. nom. max. ? 0. ? 36 bsc b 0.154 bsc c 0.01 ? 0.0 ? 0 c 0.193 bsc d 0.069 e 0.050 bsc f 0.004 0.010 g 0.016 0.050 h 0.004 0.010 0 8 symbol dimensions in mm min. nom. max. ? f 6.00 bsc b 3.90 bsc c 0.31 0.51 c 4.90 bsc d 1. ? 5 e 1. ?? bsc f 0.10 0. ? 5 g 0.40 1. ?? h 0.10 0. ? 5 0 8
rev. 1.30 108 ??? i ? ??? ? 01 ? rev. 1.30 109 ???i? ??? ?01? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom 10-pin msop outline dimensions symbol dimensions in inch min. nom. max. ? 0.043 ? 1 0.000 0.006 ?? 0.030 0.033 0.03 ? b 0.00 ? 0.013 c 0.003 0.009 d 0.118 bsc e 0.193 bsc e1 0.118 bsc e 0.0 ? 0 bsc l 0.016 0.0 ? 4 0.031 l1 0.03 ? bsc y 0.004 0 8 symbol dimensions in mm min. nom. max. ? 1.10 ? 1 0.00 0.15 ?? 0. ? 5 0.85 0.95 b 0.1 ? 0.33 c 0.08 0. ? 3 d 3.00 bsc e 4.90 bsc e1 3.00 bsc e 0.50 bsc l 0.40 0.60 0.80 l1 0.95 bsc y 0.10 0 8
rev. 1.30 108 ???i? ??? ?01? rev. 1.30 109 ??? i ? ??? ? 01 ? HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom HT66F005/ht66f006 cost-effective a/d flash mcu with eeprom co ? y ? ight ? ? 01 ? by holtek semiconductor inc. the info ? mat ion a ?? ea ? ing in this data sheet is be ? ieved to be accu ? at e at the time of ? ub ? ication. howeve ?? ho ? tek assumes no ? es ? onsibi ? ity a ? ising f ? om the use of the specifcations described. the applications mentioned herein are used solely fo ? the ? u ?? ose of i ?? ust ? ation and ho ? tek makes no wa ?? anty o ? ? e ?? esentation that such a ??? ications wi ?? be suitab ? e without fu ? the ? modification ? no ? ? ecommends the use of its ?? oducts fo ? a ??? ication that may ?? esent a ? isk to human ? ife due to ma ? function o ? ot he ? wis e. ho ? tek's ?? oduc ts a ? e not autho ? iz ed fo ? us e as c ? it ica ? com ? onents in ? ife su ?? o ? t devices o ? systems. ho ? tek ? ese ? ves the ? ight to a ? te ? its products without prior notifcation. for the most up-to-date information, please visit ou ? web site at htt ? ://www.ho ? tek.com.tw.

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